PROVIDING GUIDANCE TO AN EQUIVALENCE CHECKER WHEN A DESIGN CONTAINS RETIMED REGISTERS

Systems and techniques are described for providing guidance to an equivalence checker when a design contains retimed registers. Some embodiments can perform at least a register retiming optimization on a first design to obtain a second design. Next, the embodiments can determine one or more codes to...

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Hauptverfasser: Keladi, Sridhar, Hiraoglu, Muzaffer, Cronquist, Darren Charles, Kakkar, Navneet, Zepter, Peter Wilhelm Joseph
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creator Keladi, Sridhar
Hiraoglu, Muzaffer
Cronquist, Darren Charles
Kakkar, Navneet
Zepter, Peter Wilhelm Joseph
description Systems and techniques are described for providing guidance to an equivalence checker when a design contains retimed registers. Some embodiments can perform at least a register retiming optimization on a first design to obtain a second design. Next, the embodiments can determine one or more codes to provide guidance for connecting the set/clear inputs of the retimed registers. The first design, the second design, and the one or more codes can then be provided to an equivalence checker, wherein providing the one or more codes to the equivalence checker reduces an amount of computation required by the equivalence checker to determine functional equivalence between the first design and the second design.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2020026813A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2020026813A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2020026813A13</originalsourceid><addsrcrecordid>eNqNyk0KwjAQQOFuXIh6h4GuhTQFcRuSMRnUieanLkuRuBIt1Pujggdw9cHjzat8Cr4jQ2zBZjKKNULyoBjwnKlTB_wW7VDvMcDFIYMCg5Esg_acFHGEgImOaD5aiglDXFaz23Cfyurnoqp3mLRbl_HZl2kcruVRXn2OUkgh5GbbtKpp_7veAh0xGQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PROVIDING GUIDANCE TO AN EQUIVALENCE CHECKER WHEN A DESIGN CONTAINS RETIMED REGISTERS</title><source>esp@cenet</source><creator>Keladi, Sridhar ; Hiraoglu, Muzaffer ; Cronquist, Darren Charles ; Kakkar, Navneet ; Zepter, Peter Wilhelm Joseph</creator><creatorcontrib>Keladi, Sridhar ; Hiraoglu, Muzaffer ; Cronquist, Darren Charles ; Kakkar, Navneet ; Zepter, Peter Wilhelm Joseph</creatorcontrib><description>Systems and techniques are described for providing guidance to an equivalence checker when a design contains retimed registers. Some embodiments can perform at least a register retiming optimization on a first design to obtain a second design. Next, the embodiments can determine one or more codes to provide guidance for connecting the set/clear inputs of the retimed registers. The first design, the second design, and the one or more codes can then be provided to an equivalence checker, wherein providing the one or more codes to the equivalence checker reduces an amount of computation required by the equivalence checker to determine functional equivalence between the first design and the second design.</description><language>eng</language><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200123&amp;DB=EPODOC&amp;CC=US&amp;NR=2020026813A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200123&amp;DB=EPODOC&amp;CC=US&amp;NR=2020026813A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Keladi, Sridhar</creatorcontrib><creatorcontrib>Hiraoglu, Muzaffer</creatorcontrib><creatorcontrib>Cronquist, Darren Charles</creatorcontrib><creatorcontrib>Kakkar, Navneet</creatorcontrib><creatorcontrib>Zepter, Peter Wilhelm Joseph</creatorcontrib><title>PROVIDING GUIDANCE TO AN EQUIVALENCE CHECKER WHEN A DESIGN CONTAINS RETIMED REGISTERS</title><description>Systems and techniques are described for providing guidance to an equivalence checker when a design contains retimed registers. Some embodiments can perform at least a register retiming optimization on a first design to obtain a second design. Next, the embodiments can determine one or more codes to provide guidance for connecting the set/clear inputs of the retimed registers. The first design, the second design, and the one or more codes can then be provided to an equivalence checker, wherein providing the one or more codes to the equivalence checker reduces an amount of computation required by the equivalence checker to determine functional equivalence between the first design and the second design.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyk0KwjAQQOFuXIh6h4GuhTQFcRuSMRnUieanLkuRuBIt1Pujggdw9cHjzat8Cr4jQ2zBZjKKNULyoBjwnKlTB_wW7VDvMcDFIYMCg5Esg_acFHGEgImOaD5aiglDXFaz23Cfyurnoqp3mLRbl_HZl2kcruVRXn2OUkgh5GbbtKpp_7veAh0xGQ</recordid><startdate>20200123</startdate><enddate>20200123</enddate><creator>Keladi, Sridhar</creator><creator>Hiraoglu, Muzaffer</creator><creator>Cronquist, Darren Charles</creator><creator>Kakkar, Navneet</creator><creator>Zepter, Peter Wilhelm Joseph</creator><scope>EVB</scope></search><sort><creationdate>20200123</creationdate><title>PROVIDING GUIDANCE TO AN EQUIVALENCE CHECKER WHEN A DESIGN CONTAINS RETIMED REGISTERS</title><author>Keladi, Sridhar ; Hiraoglu, Muzaffer ; Cronquist, Darren Charles ; Kakkar, Navneet ; Zepter, Peter Wilhelm Joseph</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2020026813A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Keladi, Sridhar</creatorcontrib><creatorcontrib>Hiraoglu, Muzaffer</creatorcontrib><creatorcontrib>Cronquist, Darren Charles</creatorcontrib><creatorcontrib>Kakkar, Navneet</creatorcontrib><creatorcontrib>Zepter, Peter Wilhelm Joseph</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Keladi, Sridhar</au><au>Hiraoglu, Muzaffer</au><au>Cronquist, Darren Charles</au><au>Kakkar, Navneet</au><au>Zepter, Peter Wilhelm Joseph</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PROVIDING GUIDANCE TO AN EQUIVALENCE CHECKER WHEN A DESIGN CONTAINS RETIMED REGISTERS</title><date>2020-01-23</date><risdate>2020</risdate><abstract>Systems and techniques are described for providing guidance to an equivalence checker when a design contains retimed registers. Some embodiments can perform at least a register retiming optimization on a first design to obtain a second design. Next, the embodiments can determine one or more codes to provide guidance for connecting the set/clear inputs of the retimed registers. The first design, the second design, and the one or more codes can then be provided to an equivalence checker, wherein providing the one or more codes to the equivalence checker reduces an amount of computation required by the equivalence checker to determine functional equivalence between the first design and the second design.</abstract><oa>free_for_read</oa></addata></record>
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title PROVIDING GUIDANCE TO AN EQUIVALENCE CHECKER WHEN A DESIGN CONTAINS RETIMED REGISTERS
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T09%3A55%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Keladi,%20Sridhar&rft.date=2020-01-23&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2020026813A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true