TECHNOLOGY MAPPING METHOD OF AN FPGA

A technology mapping method for a FPGA includes converting a gate level netlist into an AND-Inverter Graph (AIG) netlist, selecting a node among nodes included in the AIG netlist, generating a cut set including one or more cuts corresponding to the selected node, selecting a best cut by sorting the...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	JO, Kangwook, YOU, Taehee, CHUNG, Eui-Young, IM, Minyoung, YOON, Hongil, KIM, Jeongbin
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE
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