PERFORMING MULTIPLY AND ACCUMULATE OPERATIONS IN NEURAL NETWORK PROCESSOR
Embodiments relate to a neural processor circuit including a plurality of neural engine circuits, a data buffer, and a kernel fetcher circuit. At least one of the neural engine circuits is configured to receive matrix elements of a matrix as at least the portion of the input data from the data buffe...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Park, Sung Hee Mills, Christopher L Norden, Erik K |
description | Embodiments relate to a neural processor circuit including a plurality of neural engine circuits, a data buffer, and a kernel fetcher circuit. At least one of the neural engine circuits is configured to receive matrix elements of a matrix as at least the portion of the input data from the data buffer over multiple processing cycles. The at least one neural engine circuit further receives vector elements of a vector from the kernel fetcher circuit, wherein each of the vector elements is extracted as a corresponding kernel to the at least one neural engine circuit in each of the processing cycles. The at least one neural engine circuit performs multiplication between the matrix and the vector as a convolution operation to produce at least one output channel of the output data. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2019340486A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2019340486A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2019340486A13</originalsourceid><addsrcrecordid>eNrjZPAMcA1y8w_y9fRzV_AN9QnxDPCJVHD0c1FwdHYOBQo4hrgq-APVOIZ4-vsFK3j6Kfi5hgY5-gCpkHD_IG-FgCB_Z9fgYP8gHgbWtMSc4lReKM3NoOzmGuLsoZtakB-fWlyQmJyal1oSHxpsZGBoaWxiYGJh5mhoTJwqAC-2Lqo</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PERFORMING MULTIPLY AND ACCUMULATE OPERATIONS IN NEURAL NETWORK PROCESSOR</title><source>esp@cenet</source><creator>Park, Sung Hee ; Mills, Christopher L ; Norden, Erik K</creator><creatorcontrib>Park, Sung Hee ; Mills, Christopher L ; Norden, Erik K</creatorcontrib><description>Embodiments relate to a neural processor circuit including a plurality of neural engine circuits, a data buffer, and a kernel fetcher circuit. At least one of the neural engine circuits is configured to receive matrix elements of a matrix as at least the portion of the input data from the data buffer over multiple processing cycles. The at least one neural engine circuit further receives vector elements of a vector from the kernel fetcher circuit, wherein each of the vector elements is extracted as a corresponding kernel to the at least one neural engine circuit in each of the processing cycles. The at least one neural engine circuit performs multiplication between the matrix and the vector as a convolution operation to produce at least one output channel of the output data.</description><language>eng</language><subject>CALCULATING ; COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20191107&DB=EPODOC&CC=US&NR=2019340486A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20191107&DB=EPODOC&CC=US&NR=2019340486A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Park, Sung Hee</creatorcontrib><creatorcontrib>Mills, Christopher L</creatorcontrib><creatorcontrib>Norden, Erik K</creatorcontrib><title>PERFORMING MULTIPLY AND ACCUMULATE OPERATIONS IN NEURAL NETWORK PROCESSOR</title><description>Embodiments relate to a neural processor circuit including a plurality of neural engine circuits, a data buffer, and a kernel fetcher circuit. At least one of the neural engine circuits is configured to receive matrix elements of a matrix as at least the portion of the input data from the data buffer over multiple processing cycles. The at least one neural engine circuit further receives vector elements of a vector from the kernel fetcher circuit, wherein each of the vector elements is extracted as a corresponding kernel to the at least one neural engine circuit in each of the processing cycles. The at least one neural engine circuit performs multiplication between the matrix and the vector as a convolution operation to produce at least one output channel of the output data.</description><subject>CALCULATING</subject><subject>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPAMcA1y8w_y9fRzV_AN9QnxDPCJVHD0c1FwdHYOBQo4hrgq-APVOIZ4-vsFK3j6Kfi5hgY5-gCpkHD_IG-FgCB_Z9fgYP8gHgbWtMSc4lReKM3NoOzmGuLsoZtakB-fWlyQmJyal1oSHxpsZGBoaWxiYGJh5mhoTJwqAC-2Lqo</recordid><startdate>20191107</startdate><enddate>20191107</enddate><creator>Park, Sung Hee</creator><creator>Mills, Christopher L</creator><creator>Norden, Erik K</creator><scope>EVB</scope></search><sort><creationdate>20191107</creationdate><title>PERFORMING MULTIPLY AND ACCUMULATE OPERATIONS IN NEURAL NETWORK PROCESSOR</title><author>Park, Sung Hee ; Mills, Christopher L ; Norden, Erik K</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019340486A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>CALCULATING</topic><topic>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Park, Sung Hee</creatorcontrib><creatorcontrib>Mills, Christopher L</creatorcontrib><creatorcontrib>Norden, Erik K</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Park, Sung Hee</au><au>Mills, Christopher L</au><au>Norden, Erik K</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PERFORMING MULTIPLY AND ACCUMULATE OPERATIONS IN NEURAL NETWORK PROCESSOR</title><date>2019-11-07</date><risdate>2019</risdate><abstract>Embodiments relate to a neural processor circuit including a plurality of neural engine circuits, a data buffer, and a kernel fetcher circuit. At least one of the neural engine circuits is configured to receive matrix elements of a matrix as at least the portion of the input data from the data buffer over multiple processing cycles. The at least one neural engine circuit further receives vector elements of a vector from the kernel fetcher circuit, wherein each of the vector elements is extracted as a corresponding kernel to the at least one neural engine circuit in each of the processing cycles. The at least one neural engine circuit performs multiplication between the matrix and the vector as a convolution operation to produce at least one output channel of the output data.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2019340486A1 |
source | esp@cenet |
subjects | CALCULATING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | PERFORMING MULTIPLY AND ACCUMULATE OPERATIONS IN NEURAL NETWORK PROCESSOR |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-29T14%3A16%3A15IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Park,%20Sung%20Hee&rft.date=2019-11-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2019340486A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |