METHODOLOGY USING FIN-FET TRANSISTORS
A computer implemented method for designing a circuit is presented. The method includes forming, using the computer, a multitude of cells. Each cell is characterized by a multitude of first shapes extending along a first direction. Each first shape is spaced, along a second direction substantially o...
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| creator | Yeap, Gary K Liu, Bohai Zhu, Chunlei Ni, Gang |
| description | A computer implemented method for designing a circuit is presented. The method includes forming, using the computer, a multitude of cells. Each cell is characterized by a multitude of first shapes extending along a first direction. Each first shape is spaced, along a second direction substantially orthogonal to the first direction, from a neighboring first shape in accordance with a first pitch. Each cell is further characterized by a cell origin including a first cell coordinate associated with the second direction. The first cell coordinate is assigned in accordance with an integer multiple of the first pitch when the computer is invoked to form the multitude of cells representing the circuit. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2019332737A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2019332737A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2019332737A13</originalsourceid><addsrcrecordid>eNrjZFD1dQ3x8Hfx9_F3j1QIDfb0c1dw8_TTdXMNUQgJcvQL9gwO8Q8K5mFgTUvMKU7lhdLcDMpAFc4euqkF-fGpxQWJyal5qSXxocFGBoaWxsZG5sbmjobGxKkCAE-0JJA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHODOLOGY USING FIN-FET TRANSISTORS</title><source>esp@cenet</source><creator>Yeap, Gary K ; Liu, Bohai ; Zhu, Chunlei ; Ni, Gang</creator><creatorcontrib>Yeap, Gary K ; Liu, Bohai ; Zhu, Chunlei ; Ni, Gang</creatorcontrib><description>A computer implemented method for designing a circuit is presented. The method includes forming, using the computer, a multitude of cells. Each cell is characterized by a multitude of first shapes extending along a first direction. Each first shape is spaced, along a second direction substantially orthogonal to the first direction, from a neighboring first shape in accordance with a first pitch. Each cell is further characterized by a cell origin including a first cell coordinate associated with the second direction. The first cell coordinate is assigned in accordance with an integer multiple of the first pitch when the computer is invoked to form the multitude of cells representing the circuit.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20191031&DB=EPODOC&CC=US&NR=2019332737A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20191031&DB=EPODOC&CC=US&NR=2019332737A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Yeap, Gary K</creatorcontrib><creatorcontrib>Liu, Bohai</creatorcontrib><creatorcontrib>Zhu, Chunlei</creatorcontrib><creatorcontrib>Ni, Gang</creatorcontrib><title>METHODOLOGY USING FIN-FET TRANSISTORS</title><description>A computer implemented method for designing a circuit is presented. The method includes forming, using the computer, a multitude of cells. Each cell is characterized by a multitude of first shapes extending along a first direction. Each first shape is spaced, along a second direction substantially orthogonal to the first direction, from a neighboring first shape in accordance with a first pitch. Each cell is further characterized by a cell origin including a first cell coordinate associated with the second direction. The first cell coordinate is assigned in accordance with an integer multiple of the first pitch when the computer is invoked to form the multitude of cells representing the circuit.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFD1dQ3x8Hfx9_F3j1QIDfb0c1dw8_TTdXMNUQgJcvQL9gwO8Q8K5mFgTUvMKU7lhdLcDMpAFc4euqkF-fGpxQWJyal5qSXxocFGBoaWxsZG5sbmjobGxKkCAE-0JJA</recordid><startdate>20191031</startdate><enddate>20191031</enddate><creator>Yeap, Gary K</creator><creator>Liu, Bohai</creator><creator>Zhu, Chunlei</creator><creator>Ni, Gang</creator><scope>EVB</scope></search><sort><creationdate>20191031</creationdate><title>METHODOLOGY USING FIN-FET TRANSISTORS</title><author>Yeap, Gary K ; Liu, Bohai ; Zhu, Chunlei ; Ni, Gang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019332737A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Yeap, Gary K</creatorcontrib><creatorcontrib>Liu, Bohai</creatorcontrib><creatorcontrib>Zhu, Chunlei</creatorcontrib><creatorcontrib>Ni, Gang</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yeap, Gary K</au><au>Liu, Bohai</au><au>Zhu, Chunlei</au><au>Ni, Gang</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHODOLOGY USING FIN-FET TRANSISTORS</title><date>2019-10-31</date><risdate>2019</risdate><abstract>A computer implemented method for designing a circuit is presented. The method includes forming, using the computer, a multitude of cells. Each cell is characterized by a multitude of first shapes extending along a first direction. Each first shape is spaced, along a second direction substantially orthogonal to the first direction, from a neighboring first shape in accordance with a first pitch. Each cell is further characterized by a cell origin including a first cell coordinate associated with the second direction. The first cell coordinate is assigned in accordance with an integer multiple of the first pitch when the computer is invoked to form the multitude of cells representing the circuit.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | METHODOLOGY USING FIN-FET TRANSISTORS |
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