FPGA Device for Image Classification
Image processing systems can include one or more cameras configured to obtain image data, one or more memory devices configured to store a classification model that classifies image features within the image data as including or not including detected objects, and a field programmable gate array (FP...
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creator | Vallespi-Gonzalez, Carlos Strother, Daniel Leland Parlour, David Bruce Totolos, JR., George Silberman, Joshua Oren |
description | Image processing systems can include one or more cameras configured to obtain image data, one or more memory devices configured to store a classification model that classifies image features within the image data as including or not including detected objects, and a field programmable gate array (FPGA) device coupled to the one or more cameras. The FPGA device is configured to implement one or more image processing pipelines for image transformation and object detection. The one or more image processing pipelines can generate a multi-scale image pyramid of multiple image samples having different scaling factors, identify and aggregate features within one or more of the multiple image samples having different scaling factors, access the classification model, provide the features as input to the classification model, and receive an output indicative of objects detected within the image data. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2019236414A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2019236414A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2019236414A13</originalsourceid><addsrcrecordid>eNrjZFBxC3B3VHBJLctMTlVIyy9S8MxNTE9VcM5JLC7OTMtMTizJzM_jYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBoaWRsZmJoYmjobGxKkCADJ2JsM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>FPGA Device for Image Classification</title><source>esp@cenet</source><creator>Vallespi-Gonzalez, Carlos ; Strother, Daniel Leland ; Parlour, David Bruce ; Totolos, JR., George ; Silberman, Joshua Oren</creator><creatorcontrib>Vallespi-Gonzalez, Carlos ; Strother, Daniel Leland ; Parlour, David Bruce ; Totolos, JR., George ; Silberman, Joshua Oren</creatorcontrib><description>Image processing systems can include one or more cameras configured to obtain image data, one or more memory devices configured to store a classification model that classifies image features within the image data as including or not including detected objects, and a field programmable gate array (FPGA) device coupled to the one or more cameras. The FPGA device is configured to implement one or more image processing pipelines for image transformation and object detection. The one or more image processing pipelines can generate a multi-scale image pyramid of multiple image samples having different scaling factors, identify and aggregate features within one or more of the multiple image samples having different scaling factors, access the classification model, provide the features as input to the classification model, and receive an output indicative of objects detected within the image data.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE ORDIFFERENT FUNCTION ; CONTROL SYSTEMS SPECIALLY ADAPTED FOR HYBRID VEHICLES ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ; PERFORMING OPERATIONS ; PHYSICS ; PICTORIAL COMMUNICATION, e.g. TELEVISION ; ROAD VEHICLE DRIVE CONTROL SYSTEMS FOR PURPOSES NOT RELATED TOTHE CONTROL OF A PARTICULAR SUB-UNIT ; TRANSPORTING ; VEHICLES IN GENERAL</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190801&DB=EPODOC&CC=US&NR=2019236414A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25547,76298</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190801&DB=EPODOC&CC=US&NR=2019236414A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Vallespi-Gonzalez, Carlos</creatorcontrib><creatorcontrib>Strother, Daniel Leland</creatorcontrib><creatorcontrib>Parlour, David Bruce</creatorcontrib><creatorcontrib>Totolos, JR., George</creatorcontrib><creatorcontrib>Silberman, Joshua Oren</creatorcontrib><title>FPGA Device for Image Classification</title><description>Image processing systems can include one or more cameras configured to obtain image data, one or more memory devices configured to store a classification model that classifies image features within the image data as including or not including detected objects, and a field programmable gate array (FPGA) device coupled to the one or more cameras. The FPGA device is configured to implement one or more image processing pipelines for image transformation and object detection. The one or more image processing pipelines can generate a multi-scale image pyramid of multiple image samples having different scaling factors, identify and aggregate features within one or more of the multiple image samples having different scaling factors, access the classification model, provide the features as input to the classification model, and receive an output indicative of objects detected within the image data.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE ORDIFFERENT FUNCTION</subject><subject>CONTROL SYSTEMS SPECIALLY ADAPTED FOR HYBRID VEHICLES</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</subject><subject>PERFORMING OPERATIONS</subject><subject>PHYSICS</subject><subject>PICTORIAL COMMUNICATION, e.g. TELEVISION</subject><subject>ROAD VEHICLE DRIVE CONTROL SYSTEMS FOR PURPOSES NOT RELATED TOTHE CONTROL OF A PARTICULAR SUB-UNIT</subject><subject>TRANSPORTING</subject><subject>VEHICLES IN GENERAL</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFBxC3B3VHBJLctMTlVIyy9S8MxNTE9VcM5JLC7OTMtMTizJzM_jYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBoaWRsZmJoYmjobGxKkCADJ2JsM</recordid><startdate>20190801</startdate><enddate>20190801</enddate><creator>Vallespi-Gonzalez, Carlos</creator><creator>Strother, Daniel Leland</creator><creator>Parlour, David Bruce</creator><creator>Totolos, JR., George</creator><creator>Silberman, Joshua Oren</creator><scope>EVB</scope></search><sort><creationdate>20190801</creationdate><title>FPGA Device for Image Classification</title><author>Vallespi-Gonzalez, Carlos ; Strother, Daniel Leland ; Parlour, David Bruce ; Totolos, JR., George ; Silberman, Joshua Oren</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019236414A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE ORDIFFERENT FUNCTION</topic><topic>CONTROL SYSTEMS SPECIALLY ADAPTED FOR HYBRID VEHICLES</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</topic><topic>PERFORMING OPERATIONS</topic><topic>PHYSICS</topic><topic>PICTORIAL COMMUNICATION, e.g. TELEVISION</topic><topic>ROAD VEHICLE DRIVE CONTROL SYSTEMS FOR PURPOSES NOT RELATED TOTHE CONTROL OF A PARTICULAR SUB-UNIT</topic><topic>TRANSPORTING</topic><topic>VEHICLES IN GENERAL</topic><toplevel>online_resources</toplevel><creatorcontrib>Vallespi-Gonzalez, Carlos</creatorcontrib><creatorcontrib>Strother, Daniel Leland</creatorcontrib><creatorcontrib>Parlour, David Bruce</creatorcontrib><creatorcontrib>Totolos, JR., George</creatorcontrib><creatorcontrib>Silberman, Joshua Oren</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Vallespi-Gonzalez, Carlos</au><au>Strother, Daniel Leland</au><au>Parlour, David Bruce</au><au>Totolos, JR., George</au><au>Silberman, Joshua Oren</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>FPGA Device for Image Classification</title><date>2019-08-01</date><risdate>2019</risdate><abstract>Image processing systems can include one or more cameras configured to obtain image data, one or more memory devices configured to store a classification model that classifies image features within the image data as including or not including detected objects, and a field programmable gate array (FPGA) device coupled to the one or more cameras. The FPGA device is configured to implement one or more image processing pipelines for image transformation and object detection. The one or more image processing pipelines can generate a multi-scale image pyramid of multiple image samples having different scaling factors, identify and aggregate features within one or more of the multiple image samples having different scaling factors, access the classification model, provide the features as input to the classification model, and receive an output indicative of objects detected within the image data.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE ORDIFFERENT FUNCTION CONTROL SYSTEMS SPECIALLY ADAPTED FOR HYBRID VEHICLES COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PERFORMING OPERATIONS PHYSICS PICTORIAL COMMUNICATION, e.g. TELEVISION ROAD VEHICLE DRIVE CONTROL SYSTEMS FOR PURPOSES NOT RELATED TOTHE CONTROL OF A PARTICULAR SUB-UNIT TRANSPORTING VEHICLES IN GENERAL |
title | FPGA Device for Image Classification |
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