Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells Individually Comprising A Programmable Charge-Storage Transistor

A method of forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising alternating insulative tiers and wordline tiers. A select gate tier is above an upper of the insulative tiers. Channel openings extend through the alternating tiers and the select gat...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Laboriante, Ian, Ng, Wei Yeeng, Greeley, Joseph Neil, John, Tom J, Hui, Ho Yee
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Laboriante, Ian
Ng, Wei Yeeng
Greeley, Joseph Neil
John, Tom J
Hui, Ho Yee
description A method of forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising alternating insulative tiers and wordline tiers. A select gate tier is above an upper of the insulative tiers. Channel openings extend through the alternating tiers and the select gate tier. Charge-storage material is formed within the channel openings elevationally along the alternating tiers and the select gate tier. Sacrificial material is formed within the channel openings laterally over the charge-storage material that is laterally over the select gate tier and that is laterally over the alternating tiers. Elevationally-outer portions of each of the charge-storage material and the sacrificial material that are within the channel openings are etched. After such etching, the sacrificial material is removed from the channel openings. After such removing, insulative charge-passage material then channel material are formed within the channel openings laterally over the charge-storage material that is laterally over the wordline tiers. The wordline tiers are formed to comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells and to have a charge-blocking region of the individual memory cells laterally between the charge-storage material and individual of the control-gate regions.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2019206884A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2019206884A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2019206884A13</originalsourceid><addsrcrecordid>eNqNjLEKwkAQRNNYiPoPC9aBREViGUKCFkEhWstq1nhwdxv2TjFf4S-biB9gNczMmxkH75L8nWsH-xsULEbZBlILqQh2Q5ZreqJXbFHrLsxfnmw9MJWXXr6zkgxLBxlp7WDX109VPwYcMjatKPf9hINwI2gMXjRBdkdpKKw8CzYER0HrlOvdNBjdUDua_XQSzIv8mG1DavlMrsUrWfLnU7WI4s0iWifJKo2X_1Efsa1PFw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells Individually Comprising A Programmable Charge-Storage Transistor</title><source>esp@cenet</source><creator>Laboriante, Ian ; Ng, Wei Yeeng ; Greeley, Joseph Neil ; John, Tom J ; Hui, Ho Yee</creator><creatorcontrib>Laboriante, Ian ; Ng, Wei Yeeng ; Greeley, Joseph Neil ; John, Tom J ; Hui, Ho Yee</creatorcontrib><description>A method of forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising alternating insulative tiers and wordline tiers. A select gate tier is above an upper of the insulative tiers. Channel openings extend through the alternating tiers and the select gate tier. Charge-storage material is formed within the channel openings elevationally along the alternating tiers and the select gate tier. Sacrificial material is formed within the channel openings laterally over the charge-storage material that is laterally over the select gate tier and that is laterally over the alternating tiers. Elevationally-outer portions of each of the charge-storage material and the sacrificial material that are within the channel openings are etched. After such etching, the sacrificial material is removed from the channel openings. After such removing, insulative charge-passage material then channel material are formed within the channel openings laterally over the charge-storage material that is laterally over the wordline tiers. The wordline tiers are formed to comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells and to have a charge-blocking region of the individual memory cells laterally between the charge-storage material and individual of the control-gate regions.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190704&amp;DB=EPODOC&amp;CC=US&amp;NR=2019206884A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190704&amp;DB=EPODOC&amp;CC=US&amp;NR=2019206884A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Laboriante, Ian</creatorcontrib><creatorcontrib>Ng, Wei Yeeng</creatorcontrib><creatorcontrib>Greeley, Joseph Neil</creatorcontrib><creatorcontrib>John, Tom J</creatorcontrib><creatorcontrib>Hui, Ho Yee</creatorcontrib><title>Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells Individually Comprising A Programmable Charge-Storage Transistor</title><description>A method of forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising alternating insulative tiers and wordline tiers. A select gate tier is above an upper of the insulative tiers. Channel openings extend through the alternating tiers and the select gate tier. Charge-storage material is formed within the channel openings elevationally along the alternating tiers and the select gate tier. Sacrificial material is formed within the channel openings laterally over the charge-storage material that is laterally over the select gate tier and that is laterally over the alternating tiers. Elevationally-outer portions of each of the charge-storage material and the sacrificial material that are within the channel openings are etched. After such etching, the sacrificial material is removed from the channel openings. After such removing, insulative charge-passage material then channel material are formed within the channel openings laterally over the charge-storage material that is laterally over the wordline tiers. The wordline tiers are formed to comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells and to have a charge-blocking region of the individual memory cells laterally between the charge-storage material and individual of the control-gate regions.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjLEKwkAQRNNYiPoPC9aBREViGUKCFkEhWstq1nhwdxv2TjFf4S-biB9gNczMmxkH75L8nWsH-xsULEbZBlILqQh2Q5ZreqJXbFHrLsxfnmw9MJWXXr6zkgxLBxlp7WDX109VPwYcMjatKPf9hINwI2gMXjRBdkdpKKw8CzYER0HrlOvdNBjdUDua_XQSzIv8mG1DavlMrsUrWfLnU7WI4s0iWifJKo2X_1Efsa1PFw</recordid><startdate>20190704</startdate><enddate>20190704</enddate><creator>Laboriante, Ian</creator><creator>Ng, Wei Yeeng</creator><creator>Greeley, Joseph Neil</creator><creator>John, Tom J</creator><creator>Hui, Ho Yee</creator><scope>EVB</scope></search><sort><creationdate>20190704</creationdate><title>Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells Individually Comprising A Programmable Charge-Storage Transistor</title><author>Laboriante, Ian ; Ng, Wei Yeeng ; Greeley, Joseph Neil ; John, Tom J ; Hui, Ho Yee</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019206884A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Laboriante, Ian</creatorcontrib><creatorcontrib>Ng, Wei Yeeng</creatorcontrib><creatorcontrib>Greeley, Joseph Neil</creatorcontrib><creatorcontrib>John, Tom J</creatorcontrib><creatorcontrib>Hui, Ho Yee</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Laboriante, Ian</au><au>Ng, Wei Yeeng</au><au>Greeley, Joseph Neil</au><au>John, Tom J</au><au>Hui, Ho Yee</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells Individually Comprising A Programmable Charge-Storage Transistor</title><date>2019-07-04</date><risdate>2019</risdate><abstract>A method of forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising alternating insulative tiers and wordline tiers. A select gate tier is above an upper of the insulative tiers. Channel openings extend through the alternating tiers and the select gate tier. Charge-storage material is formed within the channel openings elevationally along the alternating tiers and the select gate tier. Sacrificial material is formed within the channel openings laterally over the charge-storage material that is laterally over the select gate tier and that is laterally over the alternating tiers. Elevationally-outer portions of each of the charge-storage material and the sacrificial material that are within the channel openings are etched. After such etching, the sacrificial material is removed from the channel openings. After such removing, insulative charge-passage material then channel material are formed within the channel openings laterally over the charge-storage material that is laterally over the wordline tiers. The wordline tiers are formed to comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells and to have a charge-blocking region of the individual memory cells laterally between the charge-storage material and individual of the control-gate regions.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2019206884A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells Individually Comprising A Programmable Charge-Storage Transistor
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-06T23%3A55%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Laboriante,%20Ian&rft.date=2019-07-04&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2019206884A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true