GATE DRIVING CIRCUIT AND DISPLAY DEVICE HAVING THE SAME
A gate driving circuit comprising stages cascade-connected with each other and configured to output gate signals, a stage of the stages including a pull-up circuit configured to output a high voltage of a clock signal as a high voltage of a gate signal in response to a bootstrap voltage of a control...
Gespeichert in:
1. Verfasser: | |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | HWANG, Junghwan |
description | A gate driving circuit comprising stages cascade-connected with each other and configured to output gate signals, a stage of the stages including a pull-up circuit configured to output a high voltage of a clock signal as a high voltage of a gate signal in response to a bootstrap voltage of a control node in a period of a frame period, a first discharging circuit configured to discharge a voltage of the control node to a first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage, and a second discharging circuit configured to discharge a voltage of the control node to a second low voltage being lower than the first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2019206303A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2019206303A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2019206303A13</originalsourceid><addsrcrecordid>eNrjZDB3dwxxVXAJ8gzz9HNXcPYMcg71DFFw9HNRcPEMDvBxjFRwcQ3zdHZV8HAEqwjxcFUIdvR15WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgaGlkYGZsYGxo6GxsSpAgCsIiiq</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>GATE DRIVING CIRCUIT AND DISPLAY DEVICE HAVING THE SAME</title><source>esp@cenet</source><creator>HWANG, Junghwan</creator><creatorcontrib>HWANG, Junghwan</creatorcontrib><description>A gate driving circuit comprising stages cascade-connected with each other and configured to output gate signals, a stage of the stages including a pull-up circuit configured to output a high voltage of a clock signal as a high voltage of a gate signal in response to a bootstrap voltage of a control node in a period of a frame period, a first discharging circuit configured to discharge a voltage of the control node to a first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage, and a second discharging circuit configured to discharge a voltage of the control node to a second low voltage being lower than the first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage.</description><language>eng</language><subject>ADVERTISING ; ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION ; CRYPTOGRAPHY ; DISPLAY ; EDUCATION ; PHYSICS ; SEALS</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190704&DB=EPODOC&CC=US&NR=2019206303A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190704&DB=EPODOC&CC=US&NR=2019206303A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HWANG, Junghwan</creatorcontrib><title>GATE DRIVING CIRCUIT AND DISPLAY DEVICE HAVING THE SAME</title><description>A gate driving circuit comprising stages cascade-connected with each other and configured to output gate signals, a stage of the stages including a pull-up circuit configured to output a high voltage of a clock signal as a high voltage of a gate signal in response to a bootstrap voltage of a control node in a period of a frame period, a first discharging circuit configured to discharge a voltage of the control node to a first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage, and a second discharging circuit configured to discharge a voltage of the control node to a second low voltage being lower than the first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage.</description><subject>ADVERTISING</subject><subject>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</subject><subject>CRYPTOGRAPHY</subject><subject>DISPLAY</subject><subject>EDUCATION</subject><subject>PHYSICS</subject><subject>SEALS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDB3dwxxVXAJ8gzz9HNXcPYMcg71DFFw9HNRcPEMDvBxjFRwcQ3zdHZV8HAEqwjxcFUIdvR15WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgaGlkYGZsYGxo6GxsSpAgCsIiiq</recordid><startdate>20190704</startdate><enddate>20190704</enddate><creator>HWANG, Junghwan</creator><scope>EVB</scope></search><sort><creationdate>20190704</creationdate><title>GATE DRIVING CIRCUIT AND DISPLAY DEVICE HAVING THE SAME</title><author>HWANG, Junghwan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019206303A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>ADVERTISING</topic><topic>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</topic><topic>CRYPTOGRAPHY</topic><topic>DISPLAY</topic><topic>EDUCATION</topic><topic>PHYSICS</topic><topic>SEALS</topic><toplevel>online_resources</toplevel><creatorcontrib>HWANG, Junghwan</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HWANG, Junghwan</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>GATE DRIVING CIRCUIT AND DISPLAY DEVICE HAVING THE SAME</title><date>2019-07-04</date><risdate>2019</risdate><abstract>A gate driving circuit comprising stages cascade-connected with each other and configured to output gate signals, a stage of the stages including a pull-up circuit configured to output a high voltage of a clock signal as a high voltage of a gate signal in response to a bootstrap voltage of a control node in a period of a frame period, a first discharging circuit configured to discharge a voltage of the control node to a first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage, and a second discharging circuit configured to discharge a voltage of the control node to a second low voltage being lower than the first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2019206303A1 |
source | esp@cenet |
subjects | ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION CRYPTOGRAPHY DISPLAY EDUCATION PHYSICS SEALS |
title | GATE DRIVING CIRCUIT AND DISPLAY DEVICE HAVING THE SAME |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-15T19%3A41%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HWANG,%20Junghwan&rft.date=2019-07-04&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2019206303A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |