Semiconductor Package with Air Cavity
Embodiments of chip-package and corresponding methods of manufacture are provided. In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to t...
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| creator | Abdul Wahid, Junny Bakar, Roslie Saini bin Chiang, Chau Fatt Schmalzl, Stefan Tuazon Bernardez, April Coleen Othman, Nurfarena Lee, Chee Hong Chong, Hock Heng Pok, Pei Luan Kuek, Hsieh Ting Liew, Soon Lee Reiss, Werner Chua, Kok Yau Chin, Kon Hoe |
| description | Embodiments of chip-package and corresponding methods of manufacture are provided. In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either side. |
| format | Patent |
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In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either side.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190613&DB=EPODOC&CC=US&NR=2019181120A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190613&DB=EPODOC&CC=US&NR=2019181120A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Abdul Wahid, Junny</creatorcontrib><creatorcontrib>Bakar, Roslie Saini bin</creatorcontrib><creatorcontrib>Chiang, Chau Fatt</creatorcontrib><creatorcontrib>Schmalzl, Stefan</creatorcontrib><creatorcontrib>Tuazon Bernardez, April Coleen</creatorcontrib><creatorcontrib>Othman, Nurfarena</creatorcontrib><creatorcontrib>Lee, Chee Hong</creatorcontrib><creatorcontrib>Chong, Hock Heng</creatorcontrib><creatorcontrib>Pok, Pei Luan</creatorcontrib><creatorcontrib>Kuek, Hsieh Ting</creatorcontrib><creatorcontrib>Liew, Soon Lee</creatorcontrib><creatorcontrib>Reiss, Werner</creatorcontrib><creatorcontrib>Chua, Kok Yau</creatorcontrib><creatorcontrib>Chin, Kon Hoe</creatorcontrib><title>Semiconductor Package with Air Cavity</title><description>Embodiments of chip-package and corresponding methods of manufacture are provided. In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either side.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFANTs3NTM7PSylNLskvUghITM5OTE9VKM8syVBwzCxScE4syyyp5GFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgaGloYWhoZGBo6GxsSpAgDB6ifF</recordid><startdate>20190613</startdate><enddate>20190613</enddate><creator>Abdul Wahid, Junny</creator><creator>Bakar, Roslie Saini bin</creator><creator>Chiang, Chau Fatt</creator><creator>Schmalzl, Stefan</creator><creator>Tuazon Bernardez, April Coleen</creator><creator>Othman, Nurfarena</creator><creator>Lee, Chee Hong</creator><creator>Chong, Hock Heng</creator><creator>Pok, Pei Luan</creator><creator>Kuek, Hsieh Ting</creator><creator>Liew, Soon Lee</creator><creator>Reiss, Werner</creator><creator>Chua, Kok Yau</creator><creator>Chin, Kon Hoe</creator><scope>EVB</scope></search><sort><creationdate>20190613</creationdate><title>Semiconductor Package with Air Cavity</title><author>Abdul Wahid, Junny ; Bakar, Roslie Saini bin ; Chiang, Chau Fatt ; Schmalzl, Stefan ; Tuazon Bernardez, April Coleen ; Othman, Nurfarena ; Lee, Chee Hong ; Chong, Hock Heng ; Pok, Pei Luan ; Kuek, Hsieh Ting ; Liew, Soon Lee ; Reiss, Werner ; Chua, Kok Yau ; Chin, Kon Hoe</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019181120A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Abdul Wahid, Junny</creatorcontrib><creatorcontrib>Bakar, Roslie Saini bin</creatorcontrib><creatorcontrib>Chiang, Chau Fatt</creatorcontrib><creatorcontrib>Schmalzl, Stefan</creatorcontrib><creatorcontrib>Tuazon Bernardez, April Coleen</creatorcontrib><creatorcontrib>Othman, Nurfarena</creatorcontrib><creatorcontrib>Lee, Chee Hong</creatorcontrib><creatorcontrib>Chong, Hock Heng</creatorcontrib><creatorcontrib>Pok, Pei Luan</creatorcontrib><creatorcontrib>Kuek, Hsieh Ting</creatorcontrib><creatorcontrib>Liew, Soon Lee</creatorcontrib><creatorcontrib>Reiss, Werner</creatorcontrib><creatorcontrib>Chua, Kok Yau</creatorcontrib><creatorcontrib>Chin, Kon Hoe</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Abdul Wahid, Junny</au><au>Bakar, Roslie Saini bin</au><au>Chiang, Chau Fatt</au><au>Schmalzl, Stefan</au><au>Tuazon Bernardez, April Coleen</au><au>Othman, Nurfarena</au><au>Lee, Chee Hong</au><au>Chong, Hock Heng</au><au>Pok, Pei Luan</au><au>Kuek, Hsieh Ting</au><au>Liew, Soon Lee</au><au>Reiss, Werner</au><au>Chua, Kok Yau</au><au>Chin, Kon Hoe</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor Package with Air Cavity</title><date>2019-06-13</date><risdate>2019</risdate><abstract>Embodiments of chip-package and corresponding methods of manufacture are provided. In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either side.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Semiconductor Package with Air Cavity |
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