PITCH-DIVIDED INTERCONNECTS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conducti...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: MADHAVAN, Atul, AUTH, Christopher P, YEOH, Andrew W
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator MADHAVAN, Atul
AUTH, Christopher P
YEOH, Andrew W
description Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an ILD layer. The plurality of conductive interconnect lines includes a first interconnect line, and a second interconnect line immediately adjacent the first interconnect line and having a width different than a width of the first interconnect line. A third interconnect line is immediately adjacent the second interconnect line. A fourth interconnect line is immediately adjacent the third interconnect line and has a width the same as the width of the second interconnect line. A fifth interconnect line is immediately adjacent the fourth interconnect line and has a width the same as the width of the first interconnect line.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2019164890A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2019164890A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2019164890A13</originalsourceid><addsrcrecordid>eNrjZAgM8Axx9tB18QzzdHF1UfD0C3ENcvb383N1DglWcPMPUnB0CXP0c4ZKuQc5hgCZzp5BzqGeIQrBIUGhziGhQa4Kbo5OQZ7OjiGe_n48DKxpiTnFqbxQmptB2c0VZEdqQX58anFBYnJqXmpJfGiwkYGhpaGZiYWlgaOhMXGqAIZ4MKM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PITCH-DIVIDED INTERCONNECTS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION</title><source>esp@cenet</source><creator>MADHAVAN, Atul ; AUTH, Christopher P ; YEOH, Andrew W</creator><creatorcontrib>MADHAVAN, Atul ; AUTH, Christopher P ; YEOH, Andrew W</creatorcontrib><description>Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an ILD layer. The plurality of conductive interconnect lines includes a first interconnect line, and a second interconnect line immediately adjacent the first interconnect line and having a width different than a width of the first interconnect line. A third interconnect line is immediately adjacent the second interconnect line. A fourth interconnect line is immediately adjacent the third interconnect line and has a width the same as the width of the second interconnect line. A fifth interconnect line is immediately adjacent the fourth interconnect line and has a width the same as the width of the first interconnect line.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190530&amp;DB=EPODOC&amp;CC=US&amp;NR=2019164890A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190530&amp;DB=EPODOC&amp;CC=US&amp;NR=2019164890A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MADHAVAN, Atul</creatorcontrib><creatorcontrib>AUTH, Christopher P</creatorcontrib><creatorcontrib>YEOH, Andrew W</creatorcontrib><title>PITCH-DIVIDED INTERCONNECTS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION</title><description>Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an ILD layer. The plurality of conductive interconnect lines includes a first interconnect line, and a second interconnect line immediately adjacent the first interconnect line and having a width different than a width of the first interconnect line. A third interconnect line is immediately adjacent the second interconnect line. A fourth interconnect line is immediately adjacent the third interconnect line and has a width the same as the width of the second interconnect line. A fifth interconnect line is immediately adjacent the fourth interconnect line and has a width the same as the width of the first interconnect line.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAgM8Axx9tB18QzzdHF1UfD0C3ENcvb383N1DglWcPMPUnB0CXP0c4ZKuQc5hgCZzp5BzqGeIQrBIUGhziGhQa4Kbo5OQZ7OjiGe_n48DKxpiTnFqbxQmptB2c0VZEdqQX58anFBYnJqXmpJfGiwkYGhpaGZiYWlgaOhMXGqAIZ4MKM</recordid><startdate>20190530</startdate><enddate>20190530</enddate><creator>MADHAVAN, Atul</creator><creator>AUTH, Christopher P</creator><creator>YEOH, Andrew W</creator><scope>EVB</scope></search><sort><creationdate>20190530</creationdate><title>PITCH-DIVIDED INTERCONNECTS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION</title><author>MADHAVAN, Atul ; AUTH, Christopher P ; YEOH, Andrew W</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019164890A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MADHAVAN, Atul</creatorcontrib><creatorcontrib>AUTH, Christopher P</creatorcontrib><creatorcontrib>YEOH, Andrew W</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MADHAVAN, Atul</au><au>AUTH, Christopher P</au><au>YEOH, Andrew W</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PITCH-DIVIDED INTERCONNECTS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION</title><date>2019-05-30</date><risdate>2019</risdate><abstract>Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an ILD layer. The plurality of conductive interconnect lines includes a first interconnect line, and a second interconnect line immediately adjacent the first interconnect line and having a width different than a width of the first interconnect line. A third interconnect line is immediately adjacent the second interconnect line. A fourth interconnect line is immediately adjacent the third interconnect line and has a width the same as the width of the second interconnect line. A fifth interconnect line is immediately adjacent the fourth interconnect line and has a width the same as the width of the first interconnect line.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2019164890A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title PITCH-DIVIDED INTERCONNECTS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-15T00%3A52%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MADHAVAN,%20Atul&rft.date=2019-05-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2019164890A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true