Dynamic Interrupt Rate Control in Computing Systems
Systems, apparatuses, and methods for intentionally delaying servicing of interrupts in a computing system are disclosed. A computing system includes a processor that services interrupts generated by components of the computing system. An interrupt controller detects a received interrupt and intenti...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Branover, Alexander J Gada, Sridhar V |
| description | Systems, apparatuses, and methods for intentionally delaying servicing of interrupts in a computing system are disclosed. A computing system includes a processor that services interrupts generated by components of the computing system. An interrupt controller detects a received interrupt and intentionally delays servicing of the interrupt depending on various conditions. If the interrupt is a first type of interrupt and the processor is in a first power state, servicing of the interrupt is delayed by a first period of time. If the interrupt corresponds to the first type of interrupt and the processor is in a second power state, servicing of the interrupt is delayed for a period of time that is longer than the first period of time. If a non-maskable interrupt is received before expiration of either the first or second period of time, then servicing of any previously delayed interrupts is allowed to proceed. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2019163251A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2019163251A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2019163251A13</originalsourceid><addsrcrecordid>eNrjZDB2qcxLzM1MVvDMK0ktKiotKFEISixJVXDOzyspys9RyMwDMnMLSksy89IVgiuLS1Jzi3kYWNMSc4pTeaE0N4Oym2uIs4duakF-fGpxQWJyal5qSXxosJGBoaWhmbGRqaGjoTFxqgCmPC1O</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Dynamic Interrupt Rate Control in Computing Systems</title><source>esp@cenet</source><creator>Branover, Alexander J ; Gada, Sridhar V</creator><creatorcontrib>Branover, Alexander J ; Gada, Sridhar V</creatorcontrib><description>Systems, apparatuses, and methods for intentionally delaying servicing of interrupts in a computing system are disclosed. A computing system includes a processor that services interrupts generated by components of the computing system. An interrupt controller detects a received interrupt and intentionally delays servicing of the interrupt depending on various conditions. If the interrupt is a first type of interrupt and the processor is in a first power state, servicing of the interrupt is delayed by a first period of time. If the interrupt corresponds to the first type of interrupt and the processor is in a second power state, servicing of the interrupt is delayed for a period of time that is longer than the first period of time. If a non-maskable interrupt is received before expiration of either the first or second period of time, then servicing of any previously delayed interrupts is allowed to proceed.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190530&DB=EPODOC&CC=US&NR=2019163251A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190530&DB=EPODOC&CC=US&NR=2019163251A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Branover, Alexander J</creatorcontrib><creatorcontrib>Gada, Sridhar V</creatorcontrib><title>Dynamic Interrupt Rate Control in Computing Systems</title><description>Systems, apparatuses, and methods for intentionally delaying servicing of interrupts in a computing system are disclosed. A computing system includes a processor that services interrupts generated by components of the computing system. An interrupt controller detects a received interrupt and intentionally delays servicing of the interrupt depending on various conditions. If the interrupt is a first type of interrupt and the processor is in a first power state, servicing of the interrupt is delayed by a first period of time. If the interrupt corresponds to the first type of interrupt and the processor is in a second power state, servicing of the interrupt is delayed for a period of time that is longer than the first period of time. If a non-maskable interrupt is received before expiration of either the first or second period of time, then servicing of any previously delayed interrupts is allowed to proceed.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDB2qcxLzM1MVvDMK0ktKiotKFEISixJVXDOzyspys9RyMwDMnMLSksy89IVgiuLS1Jzi3kYWNMSc4pTeaE0N4Oym2uIs4duakF-fGpxQWJyal5qSXxosJGBoaWhmbGRqaGjoTFxqgCmPC1O</recordid><startdate>20190530</startdate><enddate>20190530</enddate><creator>Branover, Alexander J</creator><creator>Gada, Sridhar V</creator><scope>EVB</scope></search><sort><creationdate>20190530</creationdate><title>Dynamic Interrupt Rate Control in Computing Systems</title><author>Branover, Alexander J ; Gada, Sridhar V</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019163251A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Branover, Alexander J</creatorcontrib><creatorcontrib>Gada, Sridhar V</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Branover, Alexander J</au><au>Gada, Sridhar V</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Dynamic Interrupt Rate Control in Computing Systems</title><date>2019-05-30</date><risdate>2019</risdate><abstract>Systems, apparatuses, and methods for intentionally delaying servicing of interrupts in a computing system are disclosed. A computing system includes a processor that services interrupts generated by components of the computing system. An interrupt controller detects a received interrupt and intentionally delays servicing of the interrupt depending on various conditions. If the interrupt is a first type of interrupt and the processor is in a first power state, servicing of the interrupt is delayed by a first period of time. If the interrupt corresponds to the first type of interrupt and the processor is in a second power state, servicing of the interrupt is delayed for a period of time that is longer than the first period of time. If a non-maskable interrupt is received before expiration of either the first or second period of time, then servicing of any previously delayed interrupts is allowed to proceed.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US2019163251A1 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Dynamic Interrupt Rate Control in Computing Systems |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-22T09%3A56%3A03IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Branover,%20Alexander%20J&rft.date=2019-05-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2019163251A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |