TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT

An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	RENGARAJAN, Krishnan S, REDDY, Dhani Reddy Sreenivasula, CHANDRA, Dinesh, POTLADHURTHI, Eswararao
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
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