VIRTUAL PROCESSOR ENABLING REAL-TIME IN SITU DISASSEMBLY AND DEBUGGING IN SOC ENVIRONMENT

The example embodiments are directed to a system and method for a virtual processor that enables real-time in situ disassembly and debugging. In one example, the method includes implementing a virtual processor in field programmable gate array (FPGA) programmable logic, the virtual processor compris...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: BERNER, Andrew William, GAWRELSKI, Richard, MONG, Tab
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator BERNER, Andrew William
GAWRELSKI, Richard
MONG, Tab
description The example embodiments are directed to a system and method for a virtual processor that enables real-time in situ disassembly and debugging. In one example, the method includes implementing a virtual processor in field programmable gate array (FPGA) programmable logic, the virtual processor comprising a virtual version of a target system, capturing data representative of operations in the virtual processor using a bus access device configured to provide direct access to components of the virtual processor, streaming the data to the embedded processor, storing the data in the memory device, and performing in-situ disassembly and debugging.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2019146896A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2019146896A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2019146896A13</originalsourceid><addsrcrecordid>eNrjZIgM8wwKCXX0UQgI8nd2DQ72D1Jw9XN08vH0c1cIcnX00Q3x9HVV8PRTCPYMCVVw8Qx2DA529XXyiVRw9HNRcHF1CnV3B6kFqfB3BuoFmufv5-vqF8LDwJqWmFOcyguluRmU3VxDnD10Uwvy41OLCxKTU_NSS-JDg40MDC0NTcwsLM0cDY2JUwUA-xcyow</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>VIRTUAL PROCESSOR ENABLING REAL-TIME IN SITU DISASSEMBLY AND DEBUGGING IN SOC ENVIRONMENT</title><source>esp@cenet</source><creator>BERNER, Andrew William ; GAWRELSKI, Richard ; MONG, Tab</creator><creatorcontrib>BERNER, Andrew William ; GAWRELSKI, Richard ; MONG, Tab</creatorcontrib><description>The example embodiments are directed to a system and method for a virtual processor that enables real-time in situ disassembly and debugging. In one example, the method includes implementing a virtual processor in field programmable gate array (FPGA) programmable logic, the virtual processor comprising a virtual version of a target system, capturing data representative of operations in the virtual processor using a bus access device configured to provide direct access to components of the virtual processor, streaming the data to the embedded processor, storing the data in the memory device, and performing in-situ disassembly and debugging.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190516&amp;DB=EPODOC&amp;CC=US&amp;NR=2019146896A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190516&amp;DB=EPODOC&amp;CC=US&amp;NR=2019146896A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BERNER, Andrew William</creatorcontrib><creatorcontrib>GAWRELSKI, Richard</creatorcontrib><creatorcontrib>MONG, Tab</creatorcontrib><title>VIRTUAL PROCESSOR ENABLING REAL-TIME IN SITU DISASSEMBLY AND DEBUGGING IN SOC ENVIRONMENT</title><description>The example embodiments are directed to a system and method for a virtual processor that enables real-time in situ disassembly and debugging. In one example, the method includes implementing a virtual processor in field programmable gate array (FPGA) programmable logic, the virtual processor comprising a virtual version of a target system, capturing data representative of operations in the virtual processor using a bus access device configured to provide direct access to components of the virtual processor, streaming the data to the embedded processor, storing the data in the memory device, and performing in-situ disassembly and debugging.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZIgM8wwKCXX0UQgI8nd2DQ72D1Jw9XN08vH0c1cIcnX00Q3x9HVV8PRTCPYMCVVw8Qx2DA529XXyiVRw9HNRcHF1CnV3B6kFqfB3BuoFmufv5-vqF8LDwJqWmFOcyguluRmU3VxDnD10Uwvy41OLCxKTU_NSS-JDg40MDC0NTcwsLM0cDY2JUwUA-xcyow</recordid><startdate>20190516</startdate><enddate>20190516</enddate><creator>BERNER, Andrew William</creator><creator>GAWRELSKI, Richard</creator><creator>MONG, Tab</creator><scope>EVB</scope></search><sort><creationdate>20190516</creationdate><title>VIRTUAL PROCESSOR ENABLING REAL-TIME IN SITU DISASSEMBLY AND DEBUGGING IN SOC ENVIRONMENT</title><author>BERNER, Andrew William ; GAWRELSKI, Richard ; MONG, Tab</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019146896A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>BERNER, Andrew William</creatorcontrib><creatorcontrib>GAWRELSKI, Richard</creatorcontrib><creatorcontrib>MONG, Tab</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BERNER, Andrew William</au><au>GAWRELSKI, Richard</au><au>MONG, Tab</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>VIRTUAL PROCESSOR ENABLING REAL-TIME IN SITU DISASSEMBLY AND DEBUGGING IN SOC ENVIRONMENT</title><date>2019-05-16</date><risdate>2019</risdate><abstract>The example embodiments are directed to a system and method for a virtual processor that enables real-time in situ disassembly and debugging. In one example, the method includes implementing a virtual processor in field programmable gate array (FPGA) programmable logic, the virtual processor comprising a virtual version of a target system, capturing data representative of operations in the virtual processor using a bus access device configured to provide direct access to components of the virtual processor, streaming the data to the embedded processor, storing the data in the memory device, and performing in-situ disassembly and debugging.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2019146896A1
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title VIRTUAL PROCESSOR ENABLING REAL-TIME IN SITU DISASSEMBLY AND DEBUGGING IN SOC ENVIRONMENT
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T23%3A52%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=BERNER,%20Andrew%20William&rft.date=2019-05-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2019146896A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true