STRUCTURE TO ENABLE HIGHER CURRENT DENSITY IN INTEGRATED CIRCUIT RESISTOR
An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The integrated circuit further includes an electrically isolated thermal conduit having one or more interconnect lines in every interconnect lev...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Venugopal, Archana Kande, Dhishan |
description | An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The integrated circuit further includes an electrically isolated thermal conduit having one or more interconnect lines in every interconnect level lower than the resistor. The interconnect lines of the thermal conduit are directly connected through one or more vertical interconnects, including contacts, and possibly vias, to a gate structure located on a dielectric material over the semiconductor material of the substrate. The thermal conduit is electrically isolated from the resistor, from all active components in the integrated circuit, and from the semiconductor material of the substrate. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2019139861A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2019139861A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2019139861A13</originalsourceid><addsrcrecordid>eNqNjDEKwkAQAK-xEPUPC9aCZ0BMeW7W3IJcYG-vsApB1ko0EP-PKXyAMDDNMEvHWaWgFiHQDiiF85UgchtJAIsIJYWGUma9AacZpVaCUgPIgoUVhPI86WTtFo_hOdnm55XbXkgx7mx89zaNw91e9ulLPux97av6dPTBV_9VXxGwLnU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>STRUCTURE TO ENABLE HIGHER CURRENT DENSITY IN INTEGRATED CIRCUIT RESISTOR</title><source>esp@cenet</source><creator>Venugopal, Archana ; Kande, Dhishan</creator><creatorcontrib>Venugopal, Archana ; Kande, Dhishan</creatorcontrib><description>An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The integrated circuit further includes an electrically isolated thermal conduit having one or more interconnect lines in every interconnect level lower than the resistor. The interconnect lines of the thermal conduit are directly connected through one or more vertical interconnects, including contacts, and possibly vias, to a gate structure located on a dielectric material over the semiconductor material of the substrate. The thermal conduit is electrically isolated from the resistor, from all active components in the integrated circuit, and from the semiconductor material of the substrate.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190509&DB=EPODOC&CC=US&NR=2019139861A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190509&DB=EPODOC&CC=US&NR=2019139861A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Venugopal, Archana</creatorcontrib><creatorcontrib>Kande, Dhishan</creatorcontrib><title>STRUCTURE TO ENABLE HIGHER CURRENT DENSITY IN INTEGRATED CIRCUIT RESISTOR</title><description>An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The integrated circuit further includes an electrically isolated thermal conduit having one or more interconnect lines in every interconnect level lower than the resistor. The interconnect lines of the thermal conduit are directly connected through one or more vertical interconnects, including contacts, and possibly vias, to a gate structure located on a dielectric material over the semiconductor material of the substrate. The thermal conduit is electrically isolated from the resistor, from all active components in the integrated circuit, and from the semiconductor material of the substrate.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjDEKwkAQAK-xEPUPC9aCZ0BMeW7W3IJcYG-vsApB1ko0EP-PKXyAMDDNMEvHWaWgFiHQDiiF85UgchtJAIsIJYWGUma9AacZpVaCUgPIgoUVhPI86WTtFo_hOdnm55XbXkgx7mx89zaNw91e9ulLPux97av6dPTBV_9VXxGwLnU</recordid><startdate>20190509</startdate><enddate>20190509</enddate><creator>Venugopal, Archana</creator><creator>Kande, Dhishan</creator><scope>EVB</scope></search><sort><creationdate>20190509</creationdate><title>STRUCTURE TO ENABLE HIGHER CURRENT DENSITY IN INTEGRATED CIRCUIT RESISTOR</title><author>Venugopal, Archana ; Kande, Dhishan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019139861A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Venugopal, Archana</creatorcontrib><creatorcontrib>Kande, Dhishan</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Venugopal, Archana</au><au>Kande, Dhishan</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>STRUCTURE TO ENABLE HIGHER CURRENT DENSITY IN INTEGRATED CIRCUIT RESISTOR</title><date>2019-05-09</date><risdate>2019</risdate><abstract>An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The integrated circuit further includes an electrically isolated thermal conduit having one or more interconnect lines in every interconnect level lower than the resistor. The interconnect lines of the thermal conduit are directly connected through one or more vertical interconnects, including contacts, and possibly vias, to a gate structure located on a dielectric material over the semiconductor material of the substrate. The thermal conduit is electrically isolated from the resistor, from all active components in the integrated circuit, and from the semiconductor material of the substrate.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2019139861A1 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | STRUCTURE TO ENABLE HIGHER CURRENT DENSITY IN INTEGRATED CIRCUIT RESISTOR |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-28T17%3A17%3A29IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Venugopal,%20Archana&rft.date=2019-05-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2019139861A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |