GLITCH DETECTION IN INPUT/OUTPUT BUS

GLITCH DETECTION IN INPUT/OUTPUT BUS

A delay circuit, including a connector pad to receive a data input, a pad pin to receive a clock input having a clock edge, a first data line to receive the data input, a second data line to receive the data input, the second data line including a delay circuit that outputs a delayed data output, an...

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1. Verfasser: KIMELMAN, Paul
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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creator KIMELMAN, Paul
description A delay circuit, including a connector pad to receive a data input, a pad pin to receive a clock input having a clock edge, a first data line to receive the data input, a second data line to receive the data input, the second data line including a delay circuit that outputs a delayed data output, and at least one logic gate to accept the data input and delayed data output and output a logic state, wherein the logic state determines whether there is a glitch in the delayed data output, and wherein the delay circuit includes at least one delay element to register an output of the at least one logic gate at the clock edge to recognize the glitch.
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subjects BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
title GLITCH DETECTION IN INPUT/OUTPUT BUS
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