PARTIAL MEMORY DIE WITH INTER-PLANE RE-MAPPING
A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the...
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| creator | Rajagiri, Avinash Peesari, Srikar Sabde, Jagdish Linnen, Daniel Periyannan, Kirubakaran Ghai, Ashish Bharadwaj, Deepak Gupta, Shantanu |
| description | A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2019129861A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2019129861A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2019129861A13</originalsourceid><addsrcrecordid>eNrjZNALcAwK8XT0UfB19fUPilRw8XRVCPcM8VDw9AtxDdIN8HH0c1UIctX1dQwI8PRz52FgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgaGloZGlhZmho6GxsSpAgBuSSaa</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PARTIAL MEMORY DIE WITH INTER-PLANE RE-MAPPING</title><source>esp@cenet</source><creator>Rajagiri, Avinash ; Peesari, Srikar ; Sabde, Jagdish ; Linnen, Daniel ; Periyannan, Kirubakaran ; Ghai, Ashish ; Bharadwaj, Deepak ; Gupta, Shantanu</creator><creatorcontrib>Rajagiri, Avinash ; Peesari, Srikar ; Sabde, Jagdish ; Linnen, Daniel ; Periyannan, Kirubakaran ; Ghai, Ashish ; Bharadwaj, Deepak ; Gupta, Shantanu</creatorcontrib><description>A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190502&DB=EPODOC&CC=US&NR=2019129861A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190502&DB=EPODOC&CC=US&NR=2019129861A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Rajagiri, Avinash</creatorcontrib><creatorcontrib>Peesari, Srikar</creatorcontrib><creatorcontrib>Sabde, Jagdish</creatorcontrib><creatorcontrib>Linnen, Daniel</creatorcontrib><creatorcontrib>Periyannan, Kirubakaran</creatorcontrib><creatorcontrib>Ghai, Ashish</creatorcontrib><creatorcontrib>Bharadwaj, Deepak</creatorcontrib><creatorcontrib>Gupta, Shantanu</creatorcontrib><title>PARTIAL MEMORY DIE WITH INTER-PLANE RE-MAPPING</title><description>A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNALcAwK8XT0UfB19fUPilRw8XRVCPcM8VDw9AtxDdIN8HH0c1UIctX1dQwI8PRz52FgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgaGloZGlhZmho6GxsSpAgBuSSaa</recordid><startdate>20190502</startdate><enddate>20190502</enddate><creator>Rajagiri, Avinash</creator><creator>Peesari, Srikar</creator><creator>Sabde, Jagdish</creator><creator>Linnen, Daniel</creator><creator>Periyannan, Kirubakaran</creator><creator>Ghai, Ashish</creator><creator>Bharadwaj, Deepak</creator><creator>Gupta, Shantanu</creator><scope>EVB</scope></search><sort><creationdate>20190502</creationdate><title>PARTIAL MEMORY DIE WITH INTER-PLANE RE-MAPPING</title><author>Rajagiri, Avinash ; Peesari, Srikar ; Sabde, Jagdish ; Linnen, Daniel ; Periyannan, Kirubakaran ; Ghai, Ashish ; Bharadwaj, Deepak ; Gupta, Shantanu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019129861A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Rajagiri, Avinash</creatorcontrib><creatorcontrib>Peesari, Srikar</creatorcontrib><creatorcontrib>Sabde, Jagdish</creatorcontrib><creatorcontrib>Linnen, Daniel</creatorcontrib><creatorcontrib>Periyannan, Kirubakaran</creatorcontrib><creatorcontrib>Ghai, Ashish</creatorcontrib><creatorcontrib>Bharadwaj, Deepak</creatorcontrib><creatorcontrib>Gupta, Shantanu</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Rajagiri, Avinash</au><au>Peesari, Srikar</au><au>Sabde, Jagdish</au><au>Linnen, Daniel</au><au>Periyannan, Kirubakaran</au><au>Ghai, Ashish</au><au>Bharadwaj, Deepak</au><au>Gupta, Shantanu</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PARTIAL MEMORY DIE WITH INTER-PLANE RE-MAPPING</title><date>2019-05-02</date><risdate>2019</risdate><abstract>A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
| title | PARTIAL MEMORY DIE WITH INTER-PLANE RE-MAPPING |
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