METHOD TO COORDINATE SYSTEM BOOT AND RESET FLOWS AND IMPROVE RELIABILITY, AVAILABILITY AND SERVICEABILITY (RAS) AMONG MULTIPLE CHIPSETS

METHOD TO COORDINATE SYSTEM BOOT AND RESET FLOWS AND IMPROVE RELIABILITY, AVAILABILITY AND SERVICEABILITY (RAS) AMONG MULTIPLE CHIPSETS

Embodiments disclosed herein relate to coordinated system boot and reset flows and improve reliability, availability, and serviceability (RAS) among multiple chipsets. In an example, a system includes a master chipset having multiple interfaces, each interface to connect to one of a processor and a...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Wunderlich, Russell J, Chen, Chih-Cheh, Zhong, Tina C, Trivedi, Malay
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Embodiments disclosed herein relate to coordinated system boot and reset flows and improve reliability, availability, and serviceability (RAS) among multiple chipsets. In an example, a system includes a master chipset having multiple interfaces, each interface to connect to one of a processor and a chipset, at least one processor connected to the master chipset, at least one non-master chipset connected to the master chipset, and a sideband messaging channel connecting the master chipset and the non-master chipsets, wherein the master chipset is to probe a subset of its multiple interfaces to discover a topology of connected processors and non-master chipsets, and use the sideband messaging channel to coordinate a synchronized boot flow.