BUFFERING TRANSACTION REQUESTS TO A SUBSYSTEM VIA A BUS INTERCONNECT
Categories of transaction requests from a processor may be buffered until one or more conditions occur, rather than being immediately transferred to a bus interconnect system. Transaction request traffic between the processor and bus interconnect system may be monitored, and it may be determined whe...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Halavarthi Math Revana, Siddesh Roychowdhury, Kaustav |
description | Categories of transaction requests from a processor may be buffered until one or more conditions occur, rather than being immediately transferred to a bus interconnect system. Transaction request traffic between the processor and bus interconnect system may be monitored, and it may be determined whether a transaction request is of a first category rather than a second category. First-category bus transaction requests are stored in a buffer. Transaction request traffic between the bus interconnect system and one or more client components may also be monitored. It may be determined whether an aggregate amount of the transaction request traffic between the bus interconnect system and the client components is lower than a threshold. If the aggregate amount of the transaction request traffic between the bus interconnect system and the client components is lower than the threshold, buffered bus transaction requests may be transferred to the bus interconnect system. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2019073323A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2019073323A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2019073323A13</originalsourceid><addsrcrecordid>eNrjZHBxCnVzcw3y9HNXCAly9At2dA7x9PdTCHINDHUNDglWCPFXcFQIDnUKjgwOcfVVCPN0BPKdQoMVPP1CXIOc_f38XJ1DeBhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGhpYG5sbGRsaOhMXGqACK8LN8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>BUFFERING TRANSACTION REQUESTS TO A SUBSYSTEM VIA A BUS INTERCONNECT</title><source>esp@cenet</source><creator>Halavarthi Math Revana, Siddesh ; Roychowdhury, Kaustav</creator><creatorcontrib>Halavarthi Math Revana, Siddesh ; Roychowdhury, Kaustav</creatorcontrib><description>Categories of transaction requests from a processor may be buffered until one or more conditions occur, rather than being immediately transferred to a bus interconnect system. Transaction request traffic between the processor and bus interconnect system may be monitored, and it may be determined whether a transaction request is of a first category rather than a second category. First-category bus transaction requests are stored in a buffer. Transaction request traffic between the bus interconnect system and one or more client components may also be monitored. It may be determined whether an aggregate amount of the transaction request traffic between the bus interconnect system and the client components is lower than a threshold. If the aggregate amount of the transaction request traffic between the bus interconnect system and the client components is lower than the threshold, buffered bus transaction requests may be transferred to the bus interconnect system.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190307&DB=EPODOC&CC=US&NR=2019073323A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190307&DB=EPODOC&CC=US&NR=2019073323A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Halavarthi Math Revana, Siddesh</creatorcontrib><creatorcontrib>Roychowdhury, Kaustav</creatorcontrib><title>BUFFERING TRANSACTION REQUESTS TO A SUBSYSTEM VIA A BUS INTERCONNECT</title><description>Categories of transaction requests from a processor may be buffered until one or more conditions occur, rather than being immediately transferred to a bus interconnect system. Transaction request traffic between the processor and bus interconnect system may be monitored, and it may be determined whether a transaction request is of a first category rather than a second category. First-category bus transaction requests are stored in a buffer. Transaction request traffic between the bus interconnect system and one or more client components may also be monitored. It may be determined whether an aggregate amount of the transaction request traffic between the bus interconnect system and the client components is lower than a threshold. If the aggregate amount of the transaction request traffic between the bus interconnect system and the client components is lower than the threshold, buffered bus transaction requests may be transferred to the bus interconnect system.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHBxCnVzcw3y9HNXCAly9At2dA7x9PdTCHINDHUNDglWCPFXcFQIDnUKjgwOcfVVCPN0BPKdQoMVPP1CXIOc_f38XJ1DeBhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGhpYG5sbGRsaOhMXGqACK8LN8</recordid><startdate>20190307</startdate><enddate>20190307</enddate><creator>Halavarthi Math Revana, Siddesh</creator><creator>Roychowdhury, Kaustav</creator><scope>EVB</scope></search><sort><creationdate>20190307</creationdate><title>BUFFERING TRANSACTION REQUESTS TO A SUBSYSTEM VIA A BUS INTERCONNECT</title><author>Halavarthi Math Revana, Siddesh ; Roychowdhury, Kaustav</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019073323A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Halavarthi Math Revana, Siddesh</creatorcontrib><creatorcontrib>Roychowdhury, Kaustav</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Halavarthi Math Revana, Siddesh</au><au>Roychowdhury, Kaustav</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>BUFFERING TRANSACTION REQUESTS TO A SUBSYSTEM VIA A BUS INTERCONNECT</title><date>2019-03-07</date><risdate>2019</risdate><abstract>Categories of transaction requests from a processor may be buffered until one or more conditions occur, rather than being immediately transferred to a bus interconnect system. Transaction request traffic between the processor and bus interconnect system may be monitored, and it may be determined whether a transaction request is of a first category rather than a second category. First-category bus transaction requests are stored in a buffer. Transaction request traffic between the bus interconnect system and one or more client components may also be monitored. It may be determined whether an aggregate amount of the transaction request traffic between the bus interconnect system and the client components is lower than a threshold. If the aggregate amount of the transaction request traffic between the bus interconnect system and the client components is lower than the threshold, buffered bus transaction requests may be transferred to the bus interconnect system.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2019073323A1 |
source | esp@cenet |
subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | BUFFERING TRANSACTION REQUESTS TO A SUBSYSTEM VIA A BUS INTERCONNECT |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-27T08%3A00%3A09IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Halavarthi%20Math%20Revana,%20Siddesh&rft.date=2019-03-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2019073323A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |