PROCESSOR CORE POWER EVENT TRACING

PROCESSOR CORE POWER EVENT TRACING

A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Kazachinsky, Itamar, Vasisht, Vikas R, Kurts, Tsvika, Strong, Beeman C, Chynoweth, Michael W, Mishaeli, Michael, Lottem, Avner, Wojciechowski, Anthony, Chabukswar, Rajshree A, O'Connor, Richard B
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Kazachinsky, Itamar
Vasisht, Vikas R
Kurts, Tsvika
Strong, Beeman C
Chynoweth, Michael W
Mishaeli, Michael
Lottem, Avner
Wojciechowski, Anthony
Chabukswar, Rajshree A
O'Connor, Richard B
description A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2019050041A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2019050041A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2019050041A13</originalsourceid><addsrcrecordid>eNrjZFAKCPJ3dg0O9g9ScPYPclUI8A93DVJwDXP1C1EICXJ09vRz52FgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgaGlgamBgYmho6GxsSpAgDOOyNp</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PROCESSOR CORE POWER EVENT TRACING</title><source>esp@cenet</source><creator>Kazachinsky, Itamar ; Vasisht, Vikas R ; Kurts, Tsvika ; Strong, Beeman C ; Chynoweth, Michael W ; Mishaeli, Michael ; Lottem, Avner ; Wojciechowski, Anthony ; Chabukswar, Rajshree A ; O'Connor, Richard B</creator><creatorcontrib>Kazachinsky, Itamar ; Vasisht, Vikas R ; Kurts, Tsvika ; Strong, Beeman C ; Chynoweth, Michael W ; Mishaeli, Michael ; Lottem, Avner ; Wojciechowski, Anthony ; Chabukswar, Rajshree A ; O'Connor, Richard B</creatorcontrib><description>A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190214&amp;DB=EPODOC&amp;CC=US&amp;NR=2019050041A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190214&amp;DB=EPODOC&amp;CC=US&amp;NR=2019050041A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kazachinsky, Itamar</creatorcontrib><creatorcontrib>Vasisht, Vikas R</creatorcontrib><creatorcontrib>Kurts, Tsvika</creatorcontrib><creatorcontrib>Strong, Beeman C</creatorcontrib><creatorcontrib>Chynoweth, Michael W</creatorcontrib><creatorcontrib>Mishaeli, Michael</creatorcontrib><creatorcontrib>Lottem, Avner</creatorcontrib><creatorcontrib>Wojciechowski, Anthony</creatorcontrib><creatorcontrib>Chabukswar, Rajshree A</creatorcontrib><creatorcontrib>O'Connor, Richard B</creatorcontrib><title>PROCESSOR CORE POWER EVENT TRACING</title><description>A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAKCPJ3dg0O9g9ScPYPclUI8A93DVJwDXP1C1EICXJ09vRz52FgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgaGlgamBgYmho6GxsSpAgDOOyNp</recordid><startdate>20190214</startdate><enddate>20190214</enddate><creator>Kazachinsky, Itamar</creator><creator>Vasisht, Vikas R</creator><creator>Kurts, Tsvika</creator><creator>Strong, Beeman C</creator><creator>Chynoweth, Michael W</creator><creator>Mishaeli, Michael</creator><creator>Lottem, Avner</creator><creator>Wojciechowski, Anthony</creator><creator>Chabukswar, Rajshree A</creator><creator>O'Connor, Richard B</creator><scope>EVB</scope></search><sort><creationdate>20190214</creationdate><title>PROCESSOR CORE POWER EVENT TRACING</title><author>Kazachinsky, Itamar ; Vasisht, Vikas R ; Kurts, Tsvika ; Strong, Beeman C ; Chynoweth, Michael W ; Mishaeli, Michael ; Lottem, Avner ; Wojciechowski, Anthony ; Chabukswar, Rajshree A ; O'Connor, Richard B</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019050041A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Kazachinsky, Itamar</creatorcontrib><creatorcontrib>Vasisht, Vikas R</creatorcontrib><creatorcontrib>Kurts, Tsvika</creatorcontrib><creatorcontrib>Strong, Beeman C</creatorcontrib><creatorcontrib>Chynoweth, Michael W</creatorcontrib><creatorcontrib>Mishaeli, Michael</creatorcontrib><creatorcontrib>Lottem, Avner</creatorcontrib><creatorcontrib>Wojciechowski, Anthony</creatorcontrib><creatorcontrib>Chabukswar, Rajshree A</creatorcontrib><creatorcontrib>O'Connor, Richard B</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kazachinsky, Itamar</au><au>Vasisht, Vikas R</au><au>Kurts, Tsvika</au><au>Strong, Beeman C</au><au>Chynoweth, Michael W</au><au>Mishaeli, Michael</au><au>Lottem, Avner</au><au>Wojciechowski, Anthony</au><au>Chabukswar, Rajshree A</au><au>O'Connor, Richard B</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PROCESSOR CORE POWER EVENT TRACING</title><date>2019-02-14</date><risdate>2019</risdate><abstract>A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2019050041A1
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title PROCESSOR CORE POWER EVENT TRACING
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-29T06%3A29%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kazachinsky,%20Itamar&rft.date=2019-02-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2019050041A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true