TECHNOLOGIES FOR OPTIMIZING TRANSMITTER EQUALIZATION WITH HIGH-SPEED RETIMER

Technologies for optimizing transmitter equalization include a computing device having a data port and a retimer. The retimer includes two serial data links, a clock recovery device, and a signal repeater. One serial data link of the retimer is connected to the data port. A bit-error rate test instrument (BERT) is connected to the other serial data link of the retimer and sweeps through multiple transmitter equalization settings while sending a compliance pattern. The retimer sends back the compliance pattern in a loopback mode. The BERT measures bit-error rate data, and an optimized transmitter equalization setting is determined based on the bit-error rate data. An end device may be configured with the optimized transmitter equalization setting and may be connected to the retimer instead of the BERT. The data port may be a PCI Express port or a backplane Ethernet port. Other embodiments are described and claimed.