BACK-END MEMORY CHANNEL THAT RESIDES BETWEEN FIRST AND SECOND DIMM SLOTS AND APPLICATIONS THEREOF
A computing system is described. The computing system includes a memory controller having a double data rate memory interface. The double data rate memory interface has a first memory channel interface and a second memory channel interface. The computing system also includes a first DIMM slot and a...
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| creator | McCALL, James A AGARWAL, Rajat VERGIS, George ZIAKAS, Dimitrios ZHAO, Chong J SAH, Suneeta NALE, Bill |
| description | A computing system is described. The computing system includes a memory controller having a double data rate memory interface. The double data rate memory interface has a first memory channel interface and a second memory channel interface. The computing system also includes a first DIMM slot and a second DIMM slot. The computing system also includes a first memory channel coupled to the first memory channel interface and the first DIMM slot, wherein the first memory channel's CA and DQ wires are not coupled to the second DIMM slot. The computing system also includes a second memory channel coupled to the second memory channel interface and the second DIMM slot, wherein the second memory channel's CA and DQ wires are not coupled to the first DIMM slot. The computing system also includes a back end memory channel that is coupled to the first and second DIMM slots. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2019042162A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2019042162A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2019042162A13</originalsourceid><addsrcrecordid>eNqNjEEKwjAQAHvxIOofFjwXmiqCx22ypcEmKdkV8VSKxJNoof4fi_gATwPDMMtsqFCfcvIGHLkQr6Ab9J5akAYFIrE1xFCRXIg81DayAM41kw4zjHUOuA3CX4td11qNYoPn-UCRQr3OFvfhMaXNj6tsW5PoJk_jq0_TONzSM737M5eFOhb7Uh1KVLv_qg9DYzQ9</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>BACK-END MEMORY CHANNEL THAT RESIDES BETWEEN FIRST AND SECOND DIMM SLOTS AND APPLICATIONS THEREOF</title><source>esp@cenet</source><creator>McCALL, James A ; AGARWAL, Rajat ; VERGIS, George ; ZIAKAS, Dimitrios ; ZHAO, Chong J ; SAH, Suneeta ; NALE, Bill</creator><creatorcontrib>McCALL, James A ; AGARWAL, Rajat ; VERGIS, George ; ZIAKAS, Dimitrios ; ZHAO, Chong J ; SAH, Suneeta ; NALE, Bill</creatorcontrib><description>A computing system is described. The computing system includes a memory controller having a double data rate memory interface. The double data rate memory interface has a first memory channel interface and a second memory channel interface. The computing system also includes a first DIMM slot and a second DIMM slot. The computing system also includes a first memory channel coupled to the first memory channel interface and the first DIMM slot, wherein the first memory channel's CA and DQ wires are not coupled to the second DIMM slot. The computing system also includes a second memory channel coupled to the second memory channel interface and the second DIMM slot, wherein the second memory channel's CA and DQ wires are not coupled to the first DIMM slot. The computing system also includes a back end memory channel that is coupled to the first and second DIMM slots.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190207&DB=EPODOC&CC=US&NR=2019042162A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190207&DB=EPODOC&CC=US&NR=2019042162A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>McCALL, James A</creatorcontrib><creatorcontrib>AGARWAL, Rajat</creatorcontrib><creatorcontrib>VERGIS, George</creatorcontrib><creatorcontrib>ZIAKAS, Dimitrios</creatorcontrib><creatorcontrib>ZHAO, Chong J</creatorcontrib><creatorcontrib>SAH, Suneeta</creatorcontrib><creatorcontrib>NALE, Bill</creatorcontrib><title>BACK-END MEMORY CHANNEL THAT RESIDES BETWEEN FIRST AND SECOND DIMM SLOTS AND APPLICATIONS THEREOF</title><description>A computing system is described. The computing system includes a memory controller having a double data rate memory interface. The double data rate memory interface has a first memory channel interface and a second memory channel interface. The computing system also includes a first DIMM slot and a second DIMM slot. The computing system also includes a first memory channel coupled to the first memory channel interface and the first DIMM slot, wherein the first memory channel's CA and DQ wires are not coupled to the second DIMM slot. The computing system also includes a second memory channel coupled to the second memory channel interface and the second DIMM slot, wherein the second memory channel's CA and DQ wires are not coupled to the first DIMM slot. The computing system also includes a back end memory channel that is coupled to the first and second DIMM slots.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjEEKwjAQAHvxIOofFjwXmiqCx22ypcEmKdkV8VSKxJNoof4fi_gATwPDMMtsqFCfcvIGHLkQr6Ab9J5akAYFIrE1xFCRXIg81DayAM41kw4zjHUOuA3CX4td11qNYoPn-UCRQr3OFvfhMaXNj6tsW5PoJk_jq0_TONzSM737M5eFOhb7Uh1KVLv_qg9DYzQ9</recordid><startdate>20190207</startdate><enddate>20190207</enddate><creator>McCALL, James A</creator><creator>AGARWAL, Rajat</creator><creator>VERGIS, George</creator><creator>ZIAKAS, Dimitrios</creator><creator>ZHAO, Chong J</creator><creator>SAH, Suneeta</creator><creator>NALE, Bill</creator><scope>EVB</scope></search><sort><creationdate>20190207</creationdate><title>BACK-END MEMORY CHANNEL THAT RESIDES BETWEEN FIRST AND SECOND DIMM SLOTS AND APPLICATIONS THEREOF</title><author>McCALL, James A ; AGARWAL, Rajat ; VERGIS, George ; ZIAKAS, Dimitrios ; ZHAO, Chong J ; SAH, Suneeta ; NALE, Bill</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019042162A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>McCALL, James A</creatorcontrib><creatorcontrib>AGARWAL, Rajat</creatorcontrib><creatorcontrib>VERGIS, George</creatorcontrib><creatorcontrib>ZIAKAS, Dimitrios</creatorcontrib><creatorcontrib>ZHAO, Chong J</creatorcontrib><creatorcontrib>SAH, Suneeta</creatorcontrib><creatorcontrib>NALE, Bill</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>McCALL, James A</au><au>AGARWAL, Rajat</au><au>VERGIS, George</au><au>ZIAKAS, Dimitrios</au><au>ZHAO, Chong J</au><au>SAH, Suneeta</au><au>NALE, Bill</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>BACK-END MEMORY CHANNEL THAT RESIDES BETWEEN FIRST AND SECOND DIMM SLOTS AND APPLICATIONS THEREOF</title><date>2019-02-07</date><risdate>2019</risdate><abstract>A computing system is described. The computing system includes a memory controller having a double data rate memory interface. The double data rate memory interface has a first memory channel interface and a second memory channel interface. The computing system also includes a first DIMM slot and a second DIMM slot. The computing system also includes a first memory channel coupled to the first memory channel interface and the first DIMM slot, wherein the first memory channel's CA and DQ wires are not coupled to the second DIMM slot. The computing system also includes a second memory channel coupled to the second memory channel interface and the second DIMM slot, wherein the second memory channel's CA and DQ wires are not coupled to the first DIMM slot. The computing system also includes a back end memory channel that is coupled to the first and second DIMM slots.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | BACK-END MEMORY CHANNEL THAT RESIDES BETWEEN FIRST AND SECOND DIMM SLOTS AND APPLICATIONS THEREOF |
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