INTEGRATED SUPERCONDUCTOR DEVICE AND METHOD OF FABRICATION
An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate la...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Murphy, Paul Wang, Connie P Sullivan, Paul |
description | An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer. The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2019035518A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2019035518A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2019035518A13</originalsourceid><addsrcrecordid>eNrjZLDy9AtxdQ9yDHF1UQgODXANcvb3cwl1DvEPUnBxDfN0dlVw9HNR8HUN8fB3UfB3U3BzdArydHYM8fT342FgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgaGlgbGpqaGFo6GxsSpAgBhsin7</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>INTEGRATED SUPERCONDUCTOR DEVICE AND METHOD OF FABRICATION</title><source>esp@cenet</source><creator>Murphy, Paul ; Wang, Connie P ; Sullivan, Paul</creator><creatorcontrib>Murphy, Paul ; Wang, Connie P ; Sullivan, Paul</creatorcontrib><description>An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer. The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CABLES ; CONDUCTORS ; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ; ELECTRICITY ; EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS ; GENERATION ; INSULATORS ; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190131&DB=EPODOC&CC=US&NR=2019035518A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190131&DB=EPODOC&CC=US&NR=2019035518A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Murphy, Paul</creatorcontrib><creatorcontrib>Wang, Connie P</creatorcontrib><creatorcontrib>Sullivan, Paul</creatorcontrib><title>INTEGRATED SUPERCONDUCTOR DEVICE AND METHOD OF FABRICATION</title><description>An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer. The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CABLES</subject><subject>CONDUCTORS</subject><subject>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</subject><subject>ELECTRICITY</subject><subject>EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS</subject><subject>GENERATION</subject><subject>INSULATORS</subject><subject>SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDy9AtxdQ9yDHF1UQgODXANcvb3cwl1DvEPUnBxDfN0dlVw9HNR8HUN8fB3UfB3U3BzdArydHYM8fT342FgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgaGlgbGpqaGFo6GxsSpAgBhsin7</recordid><startdate>20190131</startdate><enddate>20190131</enddate><creator>Murphy, Paul</creator><creator>Wang, Connie P</creator><creator>Sullivan, Paul</creator><scope>EVB</scope></search><sort><creationdate>20190131</creationdate><title>INTEGRATED SUPERCONDUCTOR DEVICE AND METHOD OF FABRICATION</title><author>Murphy, Paul ; Wang, Connie P ; Sullivan, Paul</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019035518A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CABLES</topic><topic>CONDUCTORS</topic><topic>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</topic><topic>ELECTRICITY</topic><topic>EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS</topic><topic>GENERATION</topic><topic>INSULATORS</topic><topic>SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES</topic><toplevel>online_resources</toplevel><creatorcontrib>Murphy, Paul</creatorcontrib><creatorcontrib>Wang, Connie P</creatorcontrib><creatorcontrib>Sullivan, Paul</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Murphy, Paul</au><au>Wang, Connie P</au><au>Sullivan, Paul</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INTEGRATED SUPERCONDUCTOR DEVICE AND METHOD OF FABRICATION</title><date>2019-01-31</date><risdate>2019</risdate><abstract>An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer. The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2019035518A1 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS CABLES CONDUCTORS CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRICITY EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS GENERATION INSULATORS SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES |
title | INTEGRATED SUPERCONDUCTOR DEVICE AND METHOD OF FABRICATION |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-04T21%3A23%3A07IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Murphy,%20Paul&rft.date=2019-01-31&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2019035518A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |