FREQUENCY SYNTHESIS FOR MEMORY INPUT-OUTPUT OPERATIONS
A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may incl...
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creator | Skinner, Daniel Gans, Dean Chae, Moo Sung |
description | A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal. |
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The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190124&DB=EPODOC&CC=US&NR=2019027208A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190124&DB=EPODOC&CC=US&NR=2019027208A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Skinner, Daniel</creatorcontrib><creatorcontrib>Gans, Dean</creatorcontrib><creatorcontrib>Chae, Moo Sung</creatorcontrib><title>FREQUENCY SYNTHESIS FOR MEMORY INPUT-OUTPUT OPERATIONS</title><description>A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDBzC3INDHX1c45UCI70C_FwDfYMVnDzD1LwdfX1D4pU8PQLCA3R9Q8NAVIK_gGuQY4hnv5-wTwMrGmJOcWpvFCam0HZzTXE2UM3tSA_PrW4IDE5NS-1JD402MjA0NLAyNzIwMLR0Jg4VQANfSmd</recordid><startdate>20190124</startdate><enddate>20190124</enddate><creator>Skinner, Daniel</creator><creator>Gans, Dean</creator><creator>Chae, Moo Sung</creator><scope>EVB</scope></search><sort><creationdate>20190124</creationdate><title>FREQUENCY SYNTHESIS FOR MEMORY INPUT-OUTPUT OPERATIONS</title><author>Skinner, Daniel ; Gans, Dean ; Chae, Moo Sung</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019027208A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Skinner, Daniel</creatorcontrib><creatorcontrib>Gans, Dean</creatorcontrib><creatorcontrib>Chae, Moo Sung</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Skinner, Daniel</au><au>Gans, Dean</au><au>Chae, Moo Sung</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>FREQUENCY SYNTHESIS FOR MEMORY INPUT-OUTPUT OPERATIONS</title><date>2019-01-24</date><risdate>2019</risdate><abstract>A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | INFORMATION STORAGE PHYSICS STATIC STORES |
title | FREQUENCY SYNTHESIS FOR MEMORY INPUT-OUTPUT OPERATIONS |
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