NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME
Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconducto...
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creator | MUNASINGHE, Chanaka D GHANI, Tahir LATIF, Salman |
description | Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2019006362A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2019006362A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2019006362A13</originalsourceid><addsrcrecordid>eNqNyr0KwjAQAOAsDqK-w4FzoT9QcLwm1zZg7kqSFrdSJE6ihfr-uPgATt_y7dWNhbPhioweAjmrhc2oo3gwNFlN0ONkuQMjAxkIY5O1lsFTZ4UB2YCj2IuBKNBi463GSBDQ0VHtHstzS6efB3VuKeo-S-t7Ttu63NMrfeYxlHlxyfO6qkssqv_WF4TRMbE</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME</title><source>esp@cenet</source><creator>MUNASINGHE, Chanaka D ; GHANI, Tahir ; LATIF, Salman</creator><creatorcontrib>MUNASINGHE, Chanaka D ; GHANI, Tahir ; LATIF, Salman</creatorcontrib><description>Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190103&DB=EPODOC&CC=US&NR=2019006362A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,782,887,25571,76555</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190103&DB=EPODOC&CC=US&NR=2019006362A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MUNASINGHE, Chanaka D</creatorcontrib><creatorcontrib>GHANI, Tahir</creatorcontrib><creatorcontrib>LATIF, Salman</creatorcontrib><title>NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME</title><description>Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyr0KwjAQAOAsDqK-w4FzoT9QcLwm1zZg7kqSFrdSJE6ihfr-uPgATt_y7dWNhbPhioweAjmrhc2oo3gwNFlN0ONkuQMjAxkIY5O1lsFTZ4UB2YCj2IuBKNBi463GSBDQ0VHtHstzS6efB3VuKeo-S-t7Ttu63NMrfeYxlHlxyfO6qkssqv_WF4TRMbE</recordid><startdate>20190103</startdate><enddate>20190103</enddate><creator>MUNASINGHE, Chanaka D</creator><creator>GHANI, Tahir</creator><creator>LATIF, Salman</creator><scope>EVB</scope></search><sort><creationdate>20190103</creationdate><title>NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME</title><author>MUNASINGHE, Chanaka D ; GHANI, Tahir ; LATIF, Salman</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019006362A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MUNASINGHE, Chanaka D</creatorcontrib><creatorcontrib>GHANI, Tahir</creatorcontrib><creatorcontrib>LATIF, Salman</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MUNASINGHE, Chanaka D</au><au>GHANI, Tahir</au><au>LATIF, Salman</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME</title><date>2019-01-03</date><risdate>2019</risdate><abstract>Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME |
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