DUAL-RAIL DELAY INSENSITIVE ASYNCHRONOUS LOGIC PROCESSOR WITH SINGLE-RAIL SCAN SHIFT ENABLE

There is disclosed a self-timed processor. The self-timed processor includes combinatorial logic comprising multi-rail delay insensitive asynchronous logic (DIAL) to output one or more multi-rail data values to a multiplexer. It also includes a test pattern input to output a test pattern bit stream...

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Bibliographische Detailangaben

Hauptverfasser:	Cope, Bryan Garnett, Melton, Ben
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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