DYNAMIC MICROPROCESSOR GATE DESIGN TOOL FOR AREA/TIMING MARGIN CONTROL

DYNAMIC MICROPROCESSOR GATE DESIGN TOOL FOR AREA/TIMING MARGIN CONTROL

A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical...

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Hauptverfasser: Mets, Arjen A, Washburn, Cindy S, Zhou, Nancy Y, Reddy, Lakshmi N, Kazda, Michael A
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator Mets, Arjen A
Washburn, Cindy S
Zhou, Nancy Y
Reddy, Lakshmi N
Kazda, Michael A
description A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time; applying to the model, via the processor, a proposed gate change to one or more of the plurality of gates; evaluating, via the processor and an area degradation based on the proposed gate change; determining, via the processor, a margin value based on the signal transmission time and an area degradation value; and making, via the processor, a gate change decision based on the margin value.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title DYNAMIC MICROPROCESSOR GATE DESIGN TOOL FOR AREA/TIMING MARGIN CONTROL
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