FAN-OUT SEMICONDUCTOR PACKAGE

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package includes: a first connection member having a through-hole and having a passive component disposed in the first connection member; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads dispo...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: CHO, Jung Hyun, HWANG, Jun Oh, YI, Moon Hee, JUNG, Joo Hwan, BAEK, Yong Ho
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator CHO, Jung Hyun
HWANG, Jun Oh
YI, Moon Hee
JUNG, Joo Hwan
BAEK, Yong Ho
description A fan-out semiconductor package includes: a first connection member having a through-hole and having a passive component disposed in the first connection member; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed therein and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the passive component is electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2018286790A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2018286790A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2018286790A13</originalsourceid><addsrcrecordid>eNrjZJB1c_TT9Q8NUQh29fV09vdzCXUO8Q9SCHB09nZ0d-VhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGhhZGFmbmlgaOhsbEqQIAF0oiEw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>FAN-OUT SEMICONDUCTOR PACKAGE</title><source>esp@cenet</source><creator>CHO, Jung Hyun ; HWANG, Jun Oh ; YI, Moon Hee ; JUNG, Joo Hwan ; BAEK, Yong Ho</creator><creatorcontrib>CHO, Jung Hyun ; HWANG, Jun Oh ; YI, Moon Hee ; JUNG, Joo Hwan ; BAEK, Yong Ho</creatorcontrib><description>A fan-out semiconductor package includes: a first connection member having a through-hole and having a passive component disposed in the first connection member; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed therein and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the passive component is electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20181004&amp;DB=EPODOC&amp;CC=US&amp;NR=2018286790A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20181004&amp;DB=EPODOC&amp;CC=US&amp;NR=2018286790A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHO, Jung Hyun</creatorcontrib><creatorcontrib>HWANG, Jun Oh</creatorcontrib><creatorcontrib>YI, Moon Hee</creatorcontrib><creatorcontrib>JUNG, Joo Hwan</creatorcontrib><creatorcontrib>BAEK, Yong Ho</creatorcontrib><title>FAN-OUT SEMICONDUCTOR PACKAGE</title><description>A fan-out semiconductor package includes: a first connection member having a through-hole and having a passive component disposed in the first connection member; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed therein and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the passive component is electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJB1c_TT9Q8NUQh29fV09vdzCXUO8Q9SCHB09nZ0d-VhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGhhZGFmbmlgaOhsbEqQIAF0oiEw</recordid><startdate>20181004</startdate><enddate>20181004</enddate><creator>CHO, Jung Hyun</creator><creator>HWANG, Jun Oh</creator><creator>YI, Moon Hee</creator><creator>JUNG, Joo Hwan</creator><creator>BAEK, Yong Ho</creator><scope>EVB</scope></search><sort><creationdate>20181004</creationdate><title>FAN-OUT SEMICONDUCTOR PACKAGE</title><author>CHO, Jung Hyun ; HWANG, Jun Oh ; YI, Moon Hee ; JUNG, Joo Hwan ; BAEK, Yong Ho</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2018286790A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHO, Jung Hyun</creatorcontrib><creatorcontrib>HWANG, Jun Oh</creatorcontrib><creatorcontrib>YI, Moon Hee</creatorcontrib><creatorcontrib>JUNG, Joo Hwan</creatorcontrib><creatorcontrib>BAEK, Yong Ho</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHO, Jung Hyun</au><au>HWANG, Jun Oh</au><au>YI, Moon Hee</au><au>JUNG, Joo Hwan</au><au>BAEK, Yong Ho</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>FAN-OUT SEMICONDUCTOR PACKAGE</title><date>2018-10-04</date><risdate>2018</risdate><abstract>A fan-out semiconductor package includes: a first connection member having a through-hole and having a passive component disposed in the first connection member; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed therein and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the passive component is electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2018286790A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title FAN-OUT SEMICONDUCTOR PACKAGE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T14%3A07%3A21IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHO,%20Jung%20Hyun&rft.date=2018-10-04&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2018286790A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true