METHOD AND APPARATUS FOR REDUCING WRITE CONGESTION IN NON-VOLATILE MEMORY BASED LAST LEVEL CACHES

METHOD AND APPARATUS FOR REDUCING WRITE CONGESTION IN NON-VOLATILE MEMORY BASED LAST LEVEL CACHES

In one embodiment, a processor comprises a processing core, a last level cache (LLC), and a mid-level cache. The mid-level cache is to determine that an idle indicator has been set, wherein the idle indicator is set based on an amount of activity at the LLC, and based on the determination that the i...

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Bibliographische Detailangaben
Hauptverfasser: Korgaonkar, Kunal Kishore, Subramoney, Sreenivas, Liu, Huichu, Bhati, Ishwar S, Manipatruni, Sasikanth, Wang, Hong, Young, Ian A, Gaur, Jayesh, Karnik, Tanay
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:In one embodiment, a processor comprises a processing core, a last level cache (LLC), and a mid-level cache. The mid-level cache is to determine that an idle indicator has been set, wherein the idle indicator is set based on an amount of activity at the LLC, and based on the determination that the idle indicator has been set, identify a first cache line to be evicted from a first set of cache lines of the mid-level cache and send a request to write the first cache line to the LLC.