SIGNAL PROCESSING APPARATUS AND METHOD

SIGNAL PROCESSING APPARATUS AND METHOD

The present disclosure relates to a signal processing apparatus and method that enables to reduce required power. In the signal processing apparatus, a RTC of a main chip and a RTC of a power supply chip are synchronized before power supply of the main chip is stopped, and the RTC of the main chip i...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: TANAKA, KATSUYUKI, AWATA, HIDEKI, TAKAGI, YUTAKA, SHIMIZU, TOSHIMASA, HOUCHI, SUGURU, IZUMI, KEITA, KATAYAMA, YASUSHI, YOSHIMOCHI, NAOKI, OHARA, SOTARO, TAKAHASHI, HIDEKI, TAKAOKA, KATSUMI, HIDAI, GAKU
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRONIC TIME-PIECES
HOROLOGY
PHYSICS
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Beschreibung
Zusammenfassung:The present disclosure relates to a signal processing apparatus and method that enables to reduce required power. In the signal processing apparatus, a RTC of a main chip and a RTC of a power supply chip are synchronized before power supply of the main chip is stopped, and the RTC of the main chip is synchronized with the time of the RTC of the power supply chip after the power supply of the main chip is restored. In this way, the RTC uses continuous time information before and after the stop. The present disclosure is capable of being applied to, for example, a GPS module in which a digital circuit includes a plurality of chips.