INSTRUCTION AND LOGIC FOR PARALLEL MULTI-STEP POWER MANAGEMENT FLOW
A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power manageme...
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| creator | Kuzi, Tal Mulla, Dean Rajwan, Doron Szapiro, Ariel Gendler, Alexander Tell, Nir |
| description | A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases. |
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In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180614&DB=EPODOC&CC=US&NR=2018164873A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180614&DB=EPODOC&CC=US&NR=2018164873A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kuzi, Tal</creatorcontrib><creatorcontrib>Mulla, Dean</creatorcontrib><creatorcontrib>Rajwan, Doron</creatorcontrib><creatorcontrib>Szapiro, Ariel</creatorcontrib><creatorcontrib>Gendler, Alexander</creatorcontrib><creatorcontrib>Tell, Nir</creatorcontrib><title>INSTRUCTION AND LOGIC FOR PARALLEL MULTI-STEP POWER MANAGEMENT FLOW</title><description>A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHD29AsOCQp1DvH091Nw9HNR8PF393RWcPMPUghwDHL08XH1UfAN9Qnx1A0OcQ1QCPAPdw1S8HX0c3R39XX1C1Fw8_EP52FgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgaGFoZmJhbmxo6GxsSpAgDtcCyb</recordid><startdate>20180614</startdate><enddate>20180614</enddate><creator>Kuzi, Tal</creator><creator>Mulla, Dean</creator><creator>Rajwan, Doron</creator><creator>Szapiro, Ariel</creator><creator>Gendler, Alexander</creator><creator>Tell, Nir</creator><scope>EVB</scope></search><sort><creationdate>20180614</creationdate><title>INSTRUCTION AND LOGIC FOR PARALLEL MULTI-STEP POWER MANAGEMENT FLOW</title><author>Kuzi, Tal ; Mulla, Dean ; Rajwan, Doron ; Szapiro, Ariel ; Gendler, Alexander ; Tell, Nir</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2018164873A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2018</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Kuzi, Tal</creatorcontrib><creatorcontrib>Mulla, Dean</creatorcontrib><creatorcontrib>Rajwan, Doron</creatorcontrib><creatorcontrib>Szapiro, Ariel</creatorcontrib><creatorcontrib>Gendler, Alexander</creatorcontrib><creatorcontrib>Tell, Nir</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kuzi, Tal</au><au>Mulla, Dean</au><au>Rajwan, Doron</au><au>Szapiro, Ariel</au><au>Gendler, Alexander</au><au>Tell, Nir</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INSTRUCTION AND LOGIC FOR PARALLEL MULTI-STEP POWER MANAGEMENT FLOW</title><date>2018-06-14</date><risdate>2018</risdate><abstract>A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | INSTRUCTION AND LOGIC FOR PARALLEL MULTI-STEP POWER MANAGEMENT FLOW |
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