MEMORY CIRCUIT AND METHOD OF OPERATING A MEMORY CIRCUIT

In various embodiments, a memory circuit is provided. The memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, wherein each word portion is configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion comprising a plurality of overlay memory cells, wherein each of the plurality of overlay portions comprises an overlay word, wherein the memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, thereby providing, as an output of the read operation, a result of a logic operation performed on the data word and the overlay word.