Connectable Package Extender for Semiconductor Device Package

Connectable Package Extender for Semiconductor Device Package

A semiconductor packaging system includes a semiconductor device package having a semiconductor chip with two or more terminals and a protective structure encapsulating and electrically insulating the semiconductor chip. Two or more electrical conductors that are each electrically connected to one o...

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Hauptverfasser: Tan Tian San, Long Theng Chao, Goh Ming Kai Benny
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator Tan Tian San
Long Theng Chao
Goh Ming Kai Benny
description A semiconductor packaging system includes a semiconductor device package having a semiconductor chip with two or more terminals and a protective structure encapsulating and electrically insulating the semiconductor chip. Two or more electrical conductors that are each electrically connected to one of the terminals extend to an outer surface of the protective structure. A first surface feature is on an exterior surface of the semiconductor device package. The system further includes a connectable package extender having a second surface feature configured to interlock with the first surface feature when the first surface feature is mated with the second surface feature so as to secure the package extender to the semiconductor device package. An extension portion adjoins and extends away from the exterior surface of the semiconductor device package when the package extender is secured to the semiconductor device package.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2018102300A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2018102300A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2018102300A13</originalsourceid><addsrcrecordid>eNrjZLB1zs_LS00uSUzKSVUISEzOTkxPVXCtKEnNS0ktUkjLL1IITs3NTM7PSylNLgHyXFLLMpPhKnkYWNMSc4pTeaE0N4Oym2uIs4duakF-fGpxQWJyal5qSXxosJGBoYWhgZGxgYGjoTFxqgC1jzCl</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Connectable Package Extender for Semiconductor Device Package</title><source>esp@cenet</source><creator>Tan Tian San ; Long Theng Chao ; Goh Ming Kai Benny</creator><creatorcontrib>Tan Tian San ; Long Theng Chao ; Goh Ming Kai Benny</creatorcontrib><description>A semiconductor packaging system includes a semiconductor device package having a semiconductor chip with two or more terminals and a protective structure encapsulating and electrically insulating the semiconductor chip. Two or more electrical conductors that are each electrically connected to one of the terminals extend to an outer surface of the protective structure. A first surface feature is on an exterior surface of the semiconductor device package. The system further includes a connectable package extender having a second surface feature configured to interlock with the first surface feature when the first surface feature is mated with the second surface feature so as to secure the package extender to the semiconductor device package. An extension portion adjoins and extends away from the exterior surface of the semiconductor device package when the package extender is secured to the semiconductor device package.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20180412&amp;DB=EPODOC&amp;CC=US&amp;NR=2018102300A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20180412&amp;DB=EPODOC&amp;CC=US&amp;NR=2018102300A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Tan Tian San</creatorcontrib><creatorcontrib>Long Theng Chao</creatorcontrib><creatorcontrib>Goh Ming Kai Benny</creatorcontrib><title>Connectable Package Extender for Semiconductor Device Package</title><description>A semiconductor packaging system includes a semiconductor device package having a semiconductor chip with two or more terminals and a protective structure encapsulating and electrically insulating the semiconductor chip. Two or more electrical conductors that are each electrically connected to one of the terminals extend to an outer surface of the protective structure. A first surface feature is on an exterior surface of the semiconductor device package. The system further includes a connectable package extender having a second surface feature configured to interlock with the first surface feature when the first surface feature is mated with the second surface feature so as to secure the package extender to the semiconductor device package. An extension portion adjoins and extends away from the exterior surface of the semiconductor device package when the package extender is secured to the semiconductor device package.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLB1zs_LS00uSUzKSVUISEzOTkxPVXCtKEnNS0ktUkjLL1IITs3NTM7PSylNLgHyXFLLMpPhKnkYWNMSc4pTeaE0N4Oym2uIs4duakF-fGpxQWJyal5qSXxosJGBoYWhgZGxgYGjoTFxqgC1jzCl</recordid><startdate>20180412</startdate><enddate>20180412</enddate><creator>Tan Tian San</creator><creator>Long Theng Chao</creator><creator>Goh Ming Kai Benny</creator><scope>EVB</scope></search><sort><creationdate>20180412</creationdate><title>Connectable Package Extender for Semiconductor Device Package</title><author>Tan Tian San ; Long Theng Chao ; Goh Ming Kai Benny</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2018102300A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Tan Tian San</creatorcontrib><creatorcontrib>Long Theng Chao</creatorcontrib><creatorcontrib>Goh Ming Kai Benny</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tan Tian San</au><au>Long Theng Chao</au><au>Goh Ming Kai Benny</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Connectable Package Extender for Semiconductor Device Package</title><date>2018-04-12</date><risdate>2018</risdate><abstract>A semiconductor packaging system includes a semiconductor device package having a semiconductor chip with two or more terminals and a protective structure encapsulating and electrically insulating the semiconductor chip. Two or more electrical conductors that are each electrically connected to one of the terminals extend to an outer surface of the protective structure. A first surface feature is on an exterior surface of the semiconductor device package. The system further includes a connectable package extender having a second surface feature configured to interlock with the first surface feature when the first surface feature is mated with the second surface feature so as to secure the package extender to the semiconductor device package. An extension portion adjoins and extends away from the exterior surface of the semiconductor device package when the package extender is secured to the semiconductor device package.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Connectable Package Extender for Semiconductor Device Package
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T23%3A57%3A57IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Tan%20Tian%20San&rft.date=2018-04-12&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2018102300A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true