TRANSISTOR, THIN-FILM TRANSISTOR SUBSTRATE, AND LIQUID CRYSTAL DISPLAY

TRANSISTOR, THIN-FILM TRANSISTOR SUBSTRATE, AND LIQUID CRYSTAL DISPLAY

The present technique relates to a transistor that uses an oxide semiconductor as its channel layer and that is capable of suppressing fluctuations in threshold voltage, and to a thin-film transistor substrate and a liquid crystal display that include such a transistor. The transistor is configured...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: HIRANO Rii, YAMAGATA Yusuke, NAKAGAWA Naoki
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator HIRANO Rii
YAMAGATA Yusuke
NAKAGAWA Naoki
description The present technique relates to a transistor that uses an oxide semiconductor as its channel layer and that is capable of suppressing fluctuations in threshold voltage, and to a thin-film transistor substrate and a liquid crystal display that include such a transistor. The transistor is configured such that an overlap length, which is a length of overlap in plan view between the source electrode and the channel protective film in a direction from the source electrode toward the drain electrode, is longer than an overlap length, which is a length of overlap in plan view between the drain electrode and the channel protective film in a direction from the drain electrode toward the source electrode.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2018026103A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2018026103A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2018026103A13</originalsourceid><addsrcrecordid>eNrjZHALCXL0C_YMDvEP0lEI8fD003Xz9PFVQIgqBIc6BQO5Ia46Co5-Lgo-noGhni4KzkGRwSGOPgounsEBPo6RPAysaYk5xam8UJqbQdnNNcTZQze1ID8-tbggMTk1L7UkPjTYyMDQwsDIzNDA2NHQmDhVAJUvLZE</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>TRANSISTOR, THIN-FILM TRANSISTOR SUBSTRATE, AND LIQUID CRYSTAL DISPLAY</title><source>esp@cenet</source><creator>HIRANO Rii ; YAMAGATA Yusuke ; NAKAGAWA Naoki</creator><creatorcontrib>HIRANO Rii ; YAMAGATA Yusuke ; NAKAGAWA Naoki</creatorcontrib><description>The present technique relates to a transistor that uses an oxide semiconductor as its channel layer and that is capable of suppressing fluctuations in threshold voltage, and to a thin-film transistor substrate and a liquid crystal display that include such a transistor. The transistor is configured such that an overlap length, which is a length of overlap in plan view between the source electrode and the channel protective film in a direction from the source electrode toward the drain electrode, is longer than an overlap length, which is a length of overlap in plan view between the drain electrode and the channel protective film in a direction from the drain electrode toward the source electrode.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20180125&amp;DB=EPODOC&amp;CC=US&amp;NR=2018026103A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20180125&amp;DB=EPODOC&amp;CC=US&amp;NR=2018026103A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HIRANO Rii</creatorcontrib><creatorcontrib>YAMAGATA Yusuke</creatorcontrib><creatorcontrib>NAKAGAWA Naoki</creatorcontrib><title>TRANSISTOR, THIN-FILM TRANSISTOR SUBSTRATE, AND LIQUID CRYSTAL DISPLAY</title><description>The present technique relates to a transistor that uses an oxide semiconductor as its channel layer and that is capable of suppressing fluctuations in threshold voltage, and to a thin-film transistor substrate and a liquid crystal display that include such a transistor. The transistor is configured such that an overlap length, which is a length of overlap in plan view between the source electrode and the channel protective film in a direction from the source electrode toward the drain electrode, is longer than an overlap length, which is a length of overlap in plan view between the drain electrode and the channel protective film in a direction from the drain electrode toward the source electrode.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHALCXL0C_YMDvEP0lEI8fD003Xz9PFVQIgqBIc6BQO5Ia46Co5-Lgo-noGhni4KzkGRwSGOPgounsEBPo6RPAysaYk5xam8UJqbQdnNNcTZQze1ID8-tbggMTk1L7UkPjTYyMDQwsDIzNDA2NHQmDhVAJUvLZE</recordid><startdate>20180125</startdate><enddate>20180125</enddate><creator>HIRANO Rii</creator><creator>YAMAGATA Yusuke</creator><creator>NAKAGAWA Naoki</creator><scope>EVB</scope></search><sort><creationdate>20180125</creationdate><title>TRANSISTOR, THIN-FILM TRANSISTOR SUBSTRATE, AND LIQUID CRYSTAL DISPLAY</title><author>HIRANO Rii ; YAMAGATA Yusuke ; NAKAGAWA Naoki</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2018026103A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HIRANO Rii</creatorcontrib><creatorcontrib>YAMAGATA Yusuke</creatorcontrib><creatorcontrib>NAKAGAWA Naoki</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HIRANO Rii</au><au>YAMAGATA Yusuke</au><au>NAKAGAWA Naoki</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>TRANSISTOR, THIN-FILM TRANSISTOR SUBSTRATE, AND LIQUID CRYSTAL DISPLAY</title><date>2018-01-25</date><risdate>2018</risdate><abstract>The present technique relates to a transistor that uses an oxide semiconductor as its channel layer and that is capable of suppressing fluctuations in threshold voltage, and to a thin-film transistor substrate and a liquid crystal display that include such a transistor. The transistor is configured such that an overlap length, which is a length of overlap in plan view between the source electrode and the channel protective film in a direction from the source electrode toward the drain electrode, is longer than an overlap length, which is a length of overlap in plan view between the drain electrode and the channel protective film in a direction from the drain electrode toward the source electrode.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2018026103A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title TRANSISTOR, THIN-FILM TRANSISTOR SUBSTRATE, AND LIQUID CRYSTAL DISPLAY
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T20%3A15%3A37IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HIRANO%20Rii&rft.date=2018-01-25&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2018026103A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true