ELECTRONIC COMPONENT BUILT-IN SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
An electronic component built-in substrate includes a first core layer having opening, a second core layer formed on the first core layer, a third core layer formed on the second core layer and having opening, a first electronic component accommodated in the opening of the first core layer, a second...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | WATANABE Hiroyuki MANO Yasuhiko |
| description | An electronic component built-in substrate includes a first core layer having opening, a second core layer formed on the first core layer, a third core layer formed on the second core layer and having opening, a first electronic component accommodated in the opening of the first core layer, a second electronic component accommodated in the opening of the third core layer, and a first build-up structure formed on the first core layer on the opposite side of the second core layer such that the first build-up structure includes conductor layers and interlayer insulating layers, and a second build-up structure formed on the third core layer on the opposite side of the second core layer such that the second build-up structure includes conductor layers and interlayer insulating layers. The second core layer has rigidity which is higher than rigidity of the first core layer and rigidity of the third core layer. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2017256497A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2017256497A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2017256497A13</originalsourceid><addsrcrecordid>eNqNyr0KwjAQAOAuDqK-w4Fzwdaf4nhNLybQXEpymUuROIkW6vvj4gM4fcu3Lhz1pCR4tgqUd4NnYoE22V5KyxBTGyWgECB34EiM70D7AA45aVSSguUbiCGI6GhbrB7Tc8m7n5tir0mUKfP8HvMyT_f8yp8xxfpQNfX5cro2WB3_W1-0RC9Q</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>ELECTRONIC COMPONENT BUILT-IN SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME</title><source>esp@cenet</source><creator>WATANABE Hiroyuki ; MANO Yasuhiko</creator><creatorcontrib>WATANABE Hiroyuki ; MANO Yasuhiko</creatorcontrib><description>An electronic component built-in substrate includes a first core layer having opening, a second core layer formed on the first core layer, a third core layer formed on the second core layer and having opening, a first electronic component accommodated in the opening of the first core layer, a second electronic component accommodated in the opening of the third core layer, and a first build-up structure formed on the first core layer on the opposite side of the second core layer such that the first build-up structure includes conductor layers and interlayer insulating layers, and a second build-up structure formed on the third core layer on the opposite side of the second core layer such that the second build-up structure includes conductor layers and interlayer insulating layers. The second core layer has rigidity which is higher than rigidity of the first core layer and rigidity of the third core layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170907&DB=EPODOC&CC=US&NR=2017256497A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170907&DB=EPODOC&CC=US&NR=2017256497A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WATANABE Hiroyuki</creatorcontrib><creatorcontrib>MANO Yasuhiko</creatorcontrib><title>ELECTRONIC COMPONENT BUILT-IN SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME</title><description>An electronic component built-in substrate includes a first core layer having opening, a second core layer formed on the first core layer, a third core layer formed on the second core layer and having opening, a first electronic component accommodated in the opening of the first core layer, a second electronic component accommodated in the opening of the third core layer, and a first build-up structure formed on the first core layer on the opposite side of the second core layer such that the first build-up structure includes conductor layers and interlayer insulating layers, and a second build-up structure formed on the third core layer on the opposite side of the second core layer such that the second build-up structure includes conductor layers and interlayer insulating layers. The second core layer has rigidity which is higher than rigidity of the first core layer and rigidity of the third core layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyr0KwjAQAOAuDqK-w4Fzwdaf4nhNLybQXEpymUuROIkW6vvj4gM4fcu3Lhz1pCR4tgqUd4NnYoE22V5KyxBTGyWgECB34EiM70D7AA45aVSSguUbiCGI6GhbrB7Tc8m7n5tir0mUKfP8HvMyT_f8yp8xxfpQNfX5cro2WB3_W1-0RC9Q</recordid><startdate>20170907</startdate><enddate>20170907</enddate><creator>WATANABE Hiroyuki</creator><creator>MANO Yasuhiko</creator><scope>EVB</scope></search><sort><creationdate>20170907</creationdate><title>ELECTRONIC COMPONENT BUILT-IN SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME</title><author>WATANABE Hiroyuki ; MANO Yasuhiko</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2017256497A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>WATANABE Hiroyuki</creatorcontrib><creatorcontrib>MANO Yasuhiko</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WATANABE Hiroyuki</au><au>MANO Yasuhiko</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ELECTRONIC COMPONENT BUILT-IN SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME</title><date>2017-09-07</date><risdate>2017</risdate><abstract>An electronic component built-in substrate includes a first core layer having opening, a second core layer formed on the first core layer, a third core layer formed on the second core layer and having opening, a first electronic component accommodated in the opening of the first core layer, a second electronic component accommodated in the opening of the third core layer, and a first build-up structure formed on the first core layer on the opposite side of the second core layer such that the first build-up structure includes conductor layers and interlayer insulating layers, and a second build-up structure formed on the third core layer on the opposite side of the second core layer such that the second build-up structure includes conductor layers and interlayer insulating layers. The second core layer has rigidity which is higher than rigidity of the first core layer and rigidity of the third core layer.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US2017256497A1 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
| title | ELECTRONIC COMPONENT BUILT-IN SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-09T05%3A38%3A30IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=WATANABE%20Hiroyuki&rft.date=2017-09-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2017256497A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |