SWITCH IMPROVEMENT USING LAYOUT OPTIMIZATION

Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a f...

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Hauptverfasser:	Zierak Michael, Sundaram Ananth, Joseph Alvin, Konduru Srikumar, Swaminathan Balaji
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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creator	Zierak Michael Sundaram Ananth Joseph Alvin Konduru Srikumar Swaminathan Balaji
description	Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a first direction. A wiring level is formed that includes a wire coupled with the first source/drain region. The wire has a length aligned in a second direction that is different from the first direction.
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subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	SWITCH IMPROVEMENT USING LAYOUT OPTIMIZATION
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