INSTRUCTION PREFETCHER DYNAMICALLY CONTROLLED BY READILY AVAILABLE PREFETCHER ACCURACY

According to one general aspect, an apparatus mat include a branch prediction unit, a fetch unit, and a pre-fetch circuit or unit. The branch prediction unit may be configured to output a predicted instruction. The fetch unit may be configured to fetch a next instruction from a cache memory. The pre...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
1. Verfasser:	KITCHIN Paul E
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	KITCHIN Paul E
description	According to one general aspect, an apparatus mat include a branch prediction unit, a fetch unit, and a pre-fetch circuit or unit. The branch prediction unit may be configured to output a predicted instruction. The fetch unit may be configured to fetch a next instruction from a cache memory. The pre-fetcher circuit may be configured to pre- fetch a previously predicted instruction into the cache memory based upon a relationship between the predicted instruction and the next instruction.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2017199739A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2017199739A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2017199739A13</originalsourceid><addsrcrecordid>eNrjZAjz9AsOCQp1DvH091MICHJ1cw1x9nANUnCJ9HP09XR29PGJVHD29wsJ8vfxcXVRcIpUCHJ1dPEEijqGOXr6ODr5uCJrc3R2Dg1ydI7kYWBNS8wpTuWF0twMymAluqkF-fGpxQWJyal5qSXxocFGBobmhpaW5saWjobGxKkCAJdBMiE</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>INSTRUCTION PREFETCHER DYNAMICALLY CONTROLLED BY READILY AVAILABLE PREFETCHER ACCURACY</title><source>esp@cenet</source><creator>KITCHIN Paul E</creator><creatorcontrib>KITCHIN Paul E</creatorcontrib><description>According to one general aspect, an apparatus mat include a branch prediction unit, a fetch unit, and a pre-fetch circuit or unit. The branch prediction unit may be configured to output a predicted instruction. The fetch unit may be configured to fetch a next instruction from a cache memory. The pre-fetcher circuit may be configured to pre- fetch a previously predicted instruction into the cache memory based upon a relationship between the predicted instruction and the next instruction.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170713&DB=EPODOC&CC=US&NR=2017199739A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170713&DB=EPODOC&CC=US&NR=2017199739A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KITCHIN Paul E</creatorcontrib><title>INSTRUCTION PREFETCHER DYNAMICALLY CONTROLLED BY READILY AVAILABLE PREFETCHER ACCURACY</title><description>According to one general aspect, an apparatus mat include a branch prediction unit, a fetch unit, and a pre-fetch circuit or unit. The branch prediction unit may be configured to output a predicted instruction. The fetch unit may be configured to fetch a next instruction from a cache memory. The pre-fetcher circuit may be configured to pre- fetch a previously predicted instruction into the cache memory based upon a relationship between the predicted instruction and the next instruction.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAjz9AsOCQp1DvH091MICHJ1cw1x9nANUnCJ9HP09XR29PGJVHD29wsJ8vfxcXVRcIpUCHJ1dPEEijqGOXr6ODr5uCJrc3R2Dg1ydI7kYWBNS8wpTuWF0twMymAluqkF-fGpxQWJyal5qSXxocFGBobmhpaW5saWjobGxKkCAJdBMiE</recordid><startdate>20170713</startdate><enddate>20170713</enddate><creator>KITCHIN Paul E</creator><scope>EVB</scope></search><sort><creationdate>20170713</creationdate><title>INSTRUCTION PREFETCHER DYNAMICALLY CONTROLLED BY READILY AVAILABLE PREFETCHER ACCURACY</title><author>KITCHIN Paul E</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2017199739A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>KITCHIN Paul E</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KITCHIN Paul E</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INSTRUCTION PREFETCHER DYNAMICALLY CONTROLLED BY READILY AVAILABLE PREFETCHER ACCURACY</title><date>2017-07-13</date><risdate>2017</risdate><abstract>According to one general aspect, an apparatus mat include a branch prediction unit, a fetch unit, and a pre-fetch circuit or unit. The branch prediction unit may be configured to output a predicted instruction. The fetch unit may be configured to fetch a next instruction from a cache memory. The pre-fetcher circuit may be configured to pre- fetch a previously predicted instruction into the cache memory based upon a relationship between the predicted instruction and the next instruction.</abstract><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_US2017199739A1
source	esp@cenet
subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	INSTRUCTION PREFETCHER DYNAMICALLY CONTROLLED BY READILY AVAILABLE PREFETCHER ACCURACY
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T21%3A39%3A49IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KITCHIN%20Paul%20E&rft.date=2017-07-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2017199739A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true