Techniques for scalable endpoint addressing for parallel applications
Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Giefer Charles F Addison David Underwood Keith |
description | Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may use an initiator-side translation process that performs an algorithmic mapping to translate a logical process identifier (e.g., a rank/processing element) into a target physical node identifier and a target local process identifier. The initiating node may then use hardware fabric of a multi-node network to route the inter-process communication to an appropriate node. A node may receive an inter-process communication and may use a target-side translation process in hardware to translate the target virtual process identifier into a local process identifier for the node. The node may then execute an operation in accordance with the inter-process communication, such as a get or set against a memory associated with the node. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2017185563A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2017185563A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2017185563A13</originalsourceid><addsrcrecordid>eNqNyrEKwjAQANAsDqL-Q8BZMJaqq0jF3TqXM7nWg-Ny5uL_C-IHOL3lzV3XY3wKvd5ofszFWwSGB6NHSZpJqoeUCpqRTN-gUIAZ2YMqU4RKWWzpZiOw4ernwq0vXX--blDzgKYQUbAO99tuGw7h2Lb75hSa_9YHBCk0ww</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Techniques for scalable endpoint addressing for parallel applications</title><source>esp@cenet</source><creator>Giefer Charles F ; Addison David ; Underwood Keith</creator><creatorcontrib>Giefer Charles F ; Addison David ; Underwood Keith</creatorcontrib><description>Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may use an initiator-side translation process that performs an algorithmic mapping to translate a logical process identifier (e.g., a rank/processing element) into a target physical node identifier and a target local process identifier. The initiating node may then use hardware fabric of a multi-node network to route the inter-process communication to an appropriate node. A node may receive an inter-process communication and may use a target-side translation process in hardware to translate the target virtual process identifier into a local process identifier for the node. The node may then execute an operation in accordance with the inter-process communication, such as a get or set against a memory associated with the node.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170629&DB=EPODOC&CC=US&NR=2017185563A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170629&DB=EPODOC&CC=US&NR=2017185563A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Giefer Charles F</creatorcontrib><creatorcontrib>Addison David</creatorcontrib><creatorcontrib>Underwood Keith</creatorcontrib><title>Techniques for scalable endpoint addressing for parallel applications</title><description>Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may use an initiator-side translation process that performs an algorithmic mapping to translate a logical process identifier (e.g., a rank/processing element) into a target physical node identifier and a target local process identifier. The initiating node may then use hardware fabric of a multi-node network to route the inter-process communication to an appropriate node. A node may receive an inter-process communication and may use a target-side translation process in hardware to translate the target virtual process identifier into a local process identifier for the node. The node may then execute an operation in accordance with the inter-process communication, such as a get or set against a memory associated with the node.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwjAQANAsDqL-Q8BZMJaqq0jF3TqXM7nWg-Ny5uL_C-IHOL3lzV3XY3wKvd5ofszFWwSGB6NHSZpJqoeUCpqRTN-gUIAZ2YMqU4RKWWzpZiOw4ernwq0vXX--blDzgKYQUbAO99tuGw7h2Lb75hSa_9YHBCk0ww</recordid><startdate>20170629</startdate><enddate>20170629</enddate><creator>Giefer Charles F</creator><creator>Addison David</creator><creator>Underwood Keith</creator><scope>EVB</scope></search><sort><creationdate>20170629</creationdate><title>Techniques for scalable endpoint addressing for parallel applications</title><author>Giefer Charles F ; Addison David ; Underwood Keith</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2017185563A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Giefer Charles F</creatorcontrib><creatorcontrib>Addison David</creatorcontrib><creatorcontrib>Underwood Keith</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Giefer Charles F</au><au>Addison David</au><au>Underwood Keith</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Techniques for scalable endpoint addressing for parallel applications</title><date>2017-06-29</date><risdate>2017</risdate><abstract>Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may use an initiator-side translation process that performs an algorithmic mapping to translate a logical process identifier (e.g., a rank/processing element) into a target physical node identifier and a target local process identifier. The initiating node may then use hardware fabric of a multi-node network to route the inter-process communication to an appropriate node. A node may receive an inter-process communication and may use a target-side translation process in hardware to translate the target virtual process identifier into a local process identifier for the node. The node may then execute an operation in accordance with the inter-process communication, such as a get or set against a memory associated with the node.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2017185563A1 |
source | esp@cenet |
subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | Techniques for scalable endpoint addressing for parallel applications |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T14%3A15%3A32IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Giefer%20Charles%20F&rft.date=2017-06-29&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2017185563A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |