MEMORY SYSTEM

A memory system may include a first cache memory including a plurality of regions, which are accessed using a first address, and in each of which an indication of whether cached data is present and a second address are stored. A memory system may also include a second cache memory configured to be a...

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Hauptverfasser:	LEE Ho-Kyoon, KIM Seon-Wook, PARK Il
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	LEE Ho-Kyoon KIM Seon-Wook PARK Il
description	A memory system may include a first cache memory including a plurality of regions, which are accessed using a first address, and in each of which an indication of whether cached data is present and a second address are stored. A memory system may also include a second cache memory configured to be accessed using the second address stored in an accessed region of the first cache memory when, as a result of an access of the first cache memory, cached data is present. Still further, a memory system may include a main memory configured to be accessed using the first address when, as the result of the access of the first cache memory, cached data is not present.
format	Patent
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A memory system may also include a second cache memory configured to be accessed using the second address stored in an accessed region of the first cache memory when, as a result of an access of the first cache memory, cached data is present. Still further, a memory system may include a main memory configured to be accessed using the first address when, as the result of the access of the first cache memory, cached data is not present.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170629&DB=EPODOC&CC=US&NR=2017185513A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170629&DB=EPODOC&CC=US&NR=2017185513A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LEE Ho-Kyoon</creatorcontrib><creatorcontrib>KIM Seon-Wook</creatorcontrib><creatorcontrib>PARK Il</creatorcontrib><title>MEMORY SYSTEM</title><description>A memory system may include a first cache memory including a plurality of regions, which are accessed using a first address, and in each of which an indication of whether cached data is present and a second address are stored. A memory system may also include a second cache memory configured to be accessed using the second address stored in an accessed region of the first cache memory when, as a result of an access of the first cache memory, cached data is present. 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A memory system may also include a second cache memory configured to be accessed using the second address stored in an accessed region of the first cache memory when, as a result of an access of the first cache memory, cached data is present. Still further, a memory system may include a main memory configured to be accessed using the first address when, as the result of the access of the first cache memory, cached data is not present.</abstract><oa>free_for_read</oa></addata></record>
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	MEMORY SYSTEM
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