AUTOMATING SYSTEM ON A CHIP CUSTOMIZED DESIGN INTEGRATION, SPECIFICATION, AND VERIFICATION THROUGH A SINGLE, INTEGRATED SERVICE
A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate a...
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creator | ON BILL N NGUYEN GIANG HARPER JEFFREY D HIRA KALPESH RAKES JAMES M |
description | A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2017177780A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2017177780A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2017177780A13</originalsourceid><addsrcrecordid>eNqNjL0KwjAUhbs4iPoOF1wrtDrENaS3ScAmJTcp6FKKxEm0UHdf3Qyls9Ph_H3r7MuDtw332kigK3lswBrgIJRuQQRKpb5hBRWSlga08ShdmluTA7UodK3FbLmpoEO3JOCVs0GqRKOEv2C-3BOQ0HVa4DZbPYbnFHezbrJ9jV6oQxzffZzG4R5f8dMHOhYlKxlj54KXp_9WPy5lPOY</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>AUTOMATING SYSTEM ON A CHIP CUSTOMIZED DESIGN INTEGRATION, SPECIFICATION, AND VERIFICATION THROUGH A SINGLE, INTEGRATED SERVICE</title><source>esp@cenet</source><creator>ON BILL N ; NGUYEN GIANG ; HARPER JEFFREY D ; HIRA KALPESH ; RAKES JAMES M</creator><creatorcontrib>ON BILL N ; NGUYEN GIANG ; HARPER JEFFREY D ; HIRA KALPESH ; RAKES JAMES M</creatorcontrib><description>A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170622&DB=EPODOC&CC=US&NR=2017177780A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170622&DB=EPODOC&CC=US&NR=2017177780A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ON BILL N</creatorcontrib><creatorcontrib>NGUYEN GIANG</creatorcontrib><creatorcontrib>HARPER JEFFREY D</creatorcontrib><creatorcontrib>HIRA KALPESH</creatorcontrib><creatorcontrib>RAKES JAMES M</creatorcontrib><title>AUTOMATING SYSTEM ON A CHIP CUSTOMIZED DESIGN INTEGRATION, SPECIFICATION, AND VERIFICATION THROUGH A SINGLE, INTEGRATED SERVICE</title><description>A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjL0KwjAUhbs4iPoOF1wrtDrENaS3ScAmJTcp6FKKxEm0UHdf3Qyls9Ph_H3r7MuDtw332kigK3lswBrgIJRuQQRKpb5hBRWSlga08ShdmluTA7UodK3FbLmpoEO3JOCVs0GqRKOEv2C-3BOQ0HVa4DZbPYbnFHezbrJ9jV6oQxzffZzG4R5f8dMHOhYlKxlj54KXp_9WPy5lPOY</recordid><startdate>20170622</startdate><enddate>20170622</enddate><creator>ON BILL N</creator><creator>NGUYEN GIANG</creator><creator>HARPER JEFFREY D</creator><creator>HIRA KALPESH</creator><creator>RAKES JAMES M</creator><scope>EVB</scope></search><sort><creationdate>20170622</creationdate><title>AUTOMATING SYSTEM ON A CHIP CUSTOMIZED DESIGN INTEGRATION, SPECIFICATION, AND VERIFICATION THROUGH A SINGLE, INTEGRATED SERVICE</title><author>ON BILL N ; NGUYEN GIANG ; HARPER JEFFREY D ; HIRA KALPESH ; RAKES JAMES M</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2017177780A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>ON BILL N</creatorcontrib><creatorcontrib>NGUYEN GIANG</creatorcontrib><creatorcontrib>HARPER JEFFREY D</creatorcontrib><creatorcontrib>HIRA KALPESH</creatorcontrib><creatorcontrib>RAKES JAMES M</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ON BILL N</au><au>NGUYEN GIANG</au><au>HARPER JEFFREY D</au><au>HIRA KALPESH</au><au>RAKES JAMES M</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>AUTOMATING SYSTEM ON A CHIP CUSTOMIZED DESIGN INTEGRATION, SPECIFICATION, AND VERIFICATION THROUGH A SINGLE, INTEGRATED SERVICE</title><date>2017-06-22</date><risdate>2017</risdate><abstract>A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | AUTOMATING SYSTEM ON A CHIP CUSTOMIZED DESIGN INTEGRATION, SPECIFICATION, AND VERIFICATION THROUGH A SINGLE, INTEGRATED SERVICE |
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