Instructions and Logic for Load-Indices-and-Gather Operations
A processor includes an execution unit to execute instructions to load indices from an array of indices and gather elements from random locations or locations in sparse memory based on those indices. The execution unit includes logic to load, for each data element to be gathered by the instruction,...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Yount Charles R Gokhale Indraneil M Valles Antonio C Ould-Ahmed-Vall Elmoustapha |
| description | A processor includes an execution unit to execute instructions to load indices from an array of indices and gather elements from random locations or locations in sparse memory based on those indices. The execution unit includes logic to load, for each data element to be gathered by the instruction, as needed, an index value to be used in computing the address in memory of a particular data element to be gathered. The index value may be retrieved from an array of indices that is identified for the instruction. The execution unit includes logic to compute the address as the sum of a base address that is specified for the instruction and the index value that was retrieved for the data element, with or without scaling. The execution unit includes logic to store the gathered data elements in contiguous locations in a destination vector register that is specified for the instruction. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2017177363A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2017177363A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2017177363A13</originalsourceid><addsrcrecordid>eNrjZLD1zCsuKSpNLsnMzytWSMxLUfDJT89MVkjLLwKyElN0PfNSMpNTi3WBUrruiSUZqUUK_gWpRYlgDTwMrGmJOcWpvFCam0HZzTXE2UM3tSA_PrW4IDE5NS-1JD402MjA0NzQ3NzYzNjR0Jg4VQCt2TC3</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Instructions and Logic for Load-Indices-and-Gather Operations</title><source>esp@cenet</source><creator>Yount Charles R ; Gokhale Indraneil M ; Valles Antonio C ; Ould-Ahmed-Vall Elmoustapha</creator><creatorcontrib>Yount Charles R ; Gokhale Indraneil M ; Valles Antonio C ; Ould-Ahmed-Vall Elmoustapha</creatorcontrib><description>A processor includes an execution unit to execute instructions to load indices from an array of indices and gather elements from random locations or locations in sparse memory based on those indices. The execution unit includes logic to load, for each data element to be gathered by the instruction, as needed, an index value to be used in computing the address in memory of a particular data element to be gathered. The index value may be retrieved from an array of indices that is identified for the instruction. The execution unit includes logic to compute the address as the sum of a base address that is specified for the instruction and the index value that was retrieved for the data element, with or without scaling. The execution unit includes logic to store the gathered data elements in contiguous locations in a destination vector register that is specified for the instruction.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170622&DB=EPODOC&CC=US&NR=2017177363A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170622&DB=EPODOC&CC=US&NR=2017177363A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Yount Charles R</creatorcontrib><creatorcontrib>Gokhale Indraneil M</creatorcontrib><creatorcontrib>Valles Antonio C</creatorcontrib><creatorcontrib>Ould-Ahmed-Vall Elmoustapha</creatorcontrib><title>Instructions and Logic for Load-Indices-and-Gather Operations</title><description>A processor includes an execution unit to execute instructions to load indices from an array of indices and gather elements from random locations or locations in sparse memory based on those indices. The execution unit includes logic to load, for each data element to be gathered by the instruction, as needed, an index value to be used in computing the address in memory of a particular data element to be gathered. The index value may be retrieved from an array of indices that is identified for the instruction. The execution unit includes logic to compute the address as the sum of a base address that is specified for the instruction and the index value that was retrieved for the data element, with or without scaling. The execution unit includes logic to store the gathered data elements in contiguous locations in a destination vector register that is specified for the instruction.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLD1zCsuKSpNLsnMzytWSMxLUfDJT89MVkjLLwKyElN0PfNSMpNTi3WBUrruiSUZqUUK_gWpRYlgDTwMrGmJOcWpvFCam0HZzTXE2UM3tSA_PrW4IDE5NS-1JD402MjA0NzQ3NzYzNjR0Jg4VQCt2TC3</recordid><startdate>20170622</startdate><enddate>20170622</enddate><creator>Yount Charles R</creator><creator>Gokhale Indraneil M</creator><creator>Valles Antonio C</creator><creator>Ould-Ahmed-Vall Elmoustapha</creator><scope>EVB</scope></search><sort><creationdate>20170622</creationdate><title>Instructions and Logic for Load-Indices-and-Gather Operations</title><author>Yount Charles R ; Gokhale Indraneil M ; Valles Antonio C ; Ould-Ahmed-Vall Elmoustapha</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2017177363A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Yount Charles R</creatorcontrib><creatorcontrib>Gokhale Indraneil M</creatorcontrib><creatorcontrib>Valles Antonio C</creatorcontrib><creatorcontrib>Ould-Ahmed-Vall Elmoustapha</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yount Charles R</au><au>Gokhale Indraneil M</au><au>Valles Antonio C</au><au>Ould-Ahmed-Vall Elmoustapha</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Instructions and Logic for Load-Indices-and-Gather Operations</title><date>2017-06-22</date><risdate>2017</risdate><abstract>A processor includes an execution unit to execute instructions to load indices from an array of indices and gather elements from random locations or locations in sparse memory based on those indices. The execution unit includes logic to load, for each data element to be gathered by the instruction, as needed, an index value to be used in computing the address in memory of a particular data element to be gathered. The index value may be retrieved from an array of indices that is identified for the instruction. The execution unit includes logic to compute the address as the sum of a base address that is specified for the instruction and the index value that was retrieved for the data element, with or without scaling. The execution unit includes logic to store the gathered data elements in contiguous locations in a destination vector register that is specified for the instruction.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US2017177363A1 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Instructions and Logic for Load-Indices-and-Gather Operations |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-24T13%3A15%3A27IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Yount%20Charles%20R&rft.date=2017-06-22&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2017177363A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |