DISPLAY PANEL

A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an...

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Hauptverfasser:	KIM Beom Jun, SYN Seong Yeol, HYUN You Mee, HWANG Jung Hwan, LEE Bong-Jun
Format:	Patent
Sprache:	eng
Schlagworte:	ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION CRYPTOGRAPHY DISPLAY EDUCATION INFORMATION STORAGE PHYSICS SEALS STATIC STORES
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creator	KIM Beom Jun SYN Seong Yeol HYUN You Mee HWANG Jung Hwan LEE Bong-Jun
description	A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
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A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.</description><language>eng</language><subject>ADVERTISING ; ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION ; CRYPTOGRAPHY ; DISPLAY ; EDUCATION ; INFORMATION STORAGE ; PHYSICS ; SEALS ; STATIC STORES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170518&DB=EPODOC&CC=US&NR=2017140698A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170518&DB=EPODOC&CC=US&NR=2017140698A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KIM Beom Jun</creatorcontrib><creatorcontrib>SYN Seong Yeol</creatorcontrib><creatorcontrib>HYUN You Mee</creatorcontrib><creatorcontrib>HWANG Jung Hwan</creatorcontrib><creatorcontrib>LEE Bong-Jun</creatorcontrib><title>DISPLAY PANEL</title><description>A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q and an output terminal connected to a gate voltage output terminal to output a gate voltage. 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The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.</abstract><oa>free_for_read</oa></addata></record>
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subjects	ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION CRYPTOGRAPHY DISPLAY EDUCATION INFORMATION STORAGE PHYSICS SEALS STATIC STORES
title	DISPLAY PANEL
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