COMBO AMORPHOUS AND LTPS TRANSISTORS
The present disclosure generally relates to an improved large area substrate thin film transistor device, and method of fabrication thereof. More specifically, amorphous and LTPS transistors are formed by first forming an amorphous silicon layer, annealing the amorphous silicon layer to form polycry...
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creator | NUNAN Peter ZHANG Xuena |
description | The present disclosure generally relates to an improved large area substrate thin film transistor device, and method of fabrication thereof. More specifically, amorphous and LTPS transistors are formed by first forming an amorphous silicon layer, annealing the amorphous silicon layer to form polycrystalline silicon, depositing a masking layer over a first portion of the polycrystalline silicon layer, implanting a second portion of the polycrystalline silicon layer with an amorphizing species, and removing the masking layer. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2017125606A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2017125606A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2017125606A13</originalsourceid><addsrcrecordid>eNrjZFBx9vd18ldw9PUPCvDwDw1WcPRzUfAJCQhWCAly9Av2DA7xDwrmYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBobmhkamZgZmjobGxKkCACB-JCs</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>COMBO AMORPHOUS AND LTPS TRANSISTORS</title><source>esp@cenet</source><creator>NUNAN Peter ; ZHANG Xuena</creator><creatorcontrib>NUNAN Peter ; ZHANG Xuena</creatorcontrib><description>The present disclosure generally relates to an improved large area substrate thin film transistor device, and method of fabrication thereof. More specifically, amorphous and LTPS transistors are formed by first forming an amorphous silicon layer, annealing the amorphous silicon layer to form polycrystalline silicon, depositing a masking layer over a first portion of the polycrystalline silicon layer, implanting a second portion of the polycrystalline silicon layer with an amorphizing species, and removing the masking layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170504&DB=EPODOC&CC=US&NR=2017125606A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170504&DB=EPODOC&CC=US&NR=2017125606A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NUNAN Peter</creatorcontrib><creatorcontrib>ZHANG Xuena</creatorcontrib><title>COMBO AMORPHOUS AND LTPS TRANSISTORS</title><description>The present disclosure generally relates to an improved large area substrate thin film transistor device, and method of fabrication thereof. More specifically, amorphous and LTPS transistors are formed by first forming an amorphous silicon layer, annealing the amorphous silicon layer to form polycrystalline silicon, depositing a masking layer over a first portion of the polycrystalline silicon layer, implanting a second portion of the polycrystalline silicon layer with an amorphizing species, and removing the masking layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFBx9vd18ldw9PUPCvDwDw1WcPRzUfAJCQhWCAly9Av2DA7xDwrmYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBobmhkamZgZmjobGxKkCACB-JCs</recordid><startdate>20170504</startdate><enddate>20170504</enddate><creator>NUNAN Peter</creator><creator>ZHANG Xuena</creator><scope>EVB</scope></search><sort><creationdate>20170504</creationdate><title>COMBO AMORPHOUS AND LTPS TRANSISTORS</title><author>NUNAN Peter ; ZHANG Xuena</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2017125606A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>NUNAN Peter</creatorcontrib><creatorcontrib>ZHANG Xuena</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NUNAN Peter</au><au>ZHANG Xuena</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>COMBO AMORPHOUS AND LTPS TRANSISTORS</title><date>2017-05-04</date><risdate>2017</risdate><abstract>The present disclosure generally relates to an improved large area substrate thin film transistor device, and method of fabrication thereof. More specifically, amorphous and LTPS transistors are formed by first forming an amorphous silicon layer, annealing the amorphous silicon layer to form polycrystalline silicon, depositing a masking layer over a first portion of the polycrystalline silicon layer, implanting a second portion of the polycrystalline silicon layer with an amorphizing species, and removing the masking layer.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | COMBO AMORPHOUS AND LTPS TRANSISTORS |
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