METHOD AND APPARATUS FOR SELECTIVE WRITE ASSIST

Write assist circuitry is disclosed to assist a memory device in changing logical states during a write operation. The write assist circuit includes write assist circuits which can be coupled to a shared boost capacitor to provide write assistance to the memory device. The write assist circuit includes boost switch circuit to selectively couple one or more of the write assist circuits and the shared boost capacitor. The one or more write assist circuits, when coupled to the shared capacitor, provide negative bitline assistance by selectively driving one of its corresponding bitlines pairs to be negative during a write operation.