SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURES AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURES AND MANUFACTURING METHOD THEREOF

A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. The fin structure has a top surface and side surfaces and the top surface is located at a height H0 measured from the substrate. An insulating layer is formed over the fin structure and the substrate...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: CHAO Yuan-Shun, CHEN Hou-Yu, TSAO Chih-Pin
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator CHAO Yuan-Shun
CHEN Hou-Yu
TSAO Chih-Pin
description A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. The fin structure has a top surface and side surfaces and the top surface is located at a height H0 measured from the substrate. An insulating layer is formed over the fin structure and the substrate. In the first recessing, the insulating layer is recessed to a height T1 from the substrate, so that an upper portion of the fin structure is exposed from the insulating layer. A semiconductor layer is formed over the exposed upper portion. After forming the semiconductor layer, in the second recessing, the insulating layer is recessed to a height T2 from the substrate, so that a middle portion of the fin structure is exposed from the insulating layer. A gate structure is formed over the upper portion with the semiconductor layer and the exposed middle portion of the fin structure.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2017092770A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2017092770A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2017092770A13</originalsourceid><addsrcrecordid>eNqNijEKAjEQANNYiPqHBWshdxbBMiQbEzAbSDa2xyGxEj04_48e-ACrgZlZCyoYg0lkq-GUweI1GIRA5lJtoDO4QFA4f2vNWECThaipOr2IZYjIPllgjxmT24rVfXzMbffjRuwdsvGHNr2GNk_jrT3be6ill52Sp14pqbvjf9cHA30v0Q</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURES AND MANUFACTURING METHOD THEREOF</title><source>esp@cenet</source><creator>CHAO Yuan-Shun ; CHEN Hou-Yu ; TSAO Chih-Pin</creator><creatorcontrib>CHAO Yuan-Shun ; CHEN Hou-Yu ; TSAO Chih-Pin</creatorcontrib><description>A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. The fin structure has a top surface and side surfaces and the top surface is located at a height H0 measured from the substrate. An insulating layer is formed over the fin structure and the substrate. In the first recessing, the insulating layer is recessed to a height T1 from the substrate, so that an upper portion of the fin structure is exposed from the insulating layer. A semiconductor layer is formed over the exposed upper portion. After forming the semiconductor layer, in the second recessing, the insulating layer is recessed to a height T2 from the substrate, so that a middle portion of the fin structure is exposed from the insulating layer. A gate structure is formed over the upper portion with the semiconductor layer and the exposed middle portion of the fin structure.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170330&amp;DB=EPODOC&amp;CC=US&amp;NR=2017092770A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170330&amp;DB=EPODOC&amp;CC=US&amp;NR=2017092770A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHAO Yuan-Shun</creatorcontrib><creatorcontrib>CHEN Hou-Yu</creatorcontrib><creatorcontrib>TSAO Chih-Pin</creatorcontrib><title>SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURES AND MANUFACTURING METHOD THEREOF</title><description>A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. The fin structure has a top surface and side surfaces and the top surface is located at a height H0 measured from the substrate. An insulating layer is formed over the fin structure and the substrate. In the first recessing, the insulating layer is recessed to a height T1 from the substrate, so that an upper portion of the fin structure is exposed from the insulating layer. A semiconductor layer is formed over the exposed upper portion. After forming the semiconductor layer, in the second recessing, the insulating layer is recessed to a height T2 from the substrate, so that a middle portion of the fin structure is exposed from the insulating layer. A gate structure is formed over the upper portion with the semiconductor layer and the exposed middle portion of the fin structure.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNijEKAjEQANNYiPqHBWshdxbBMiQbEzAbSDa2xyGxEj04_48e-ACrgZlZCyoYg0lkq-GUweI1GIRA5lJtoDO4QFA4f2vNWECThaipOr2IZYjIPllgjxmT24rVfXzMbffjRuwdsvGHNr2GNk_jrT3be6ill52Sp14pqbvjf9cHA30v0Q</recordid><startdate>20170330</startdate><enddate>20170330</enddate><creator>CHAO Yuan-Shun</creator><creator>CHEN Hou-Yu</creator><creator>TSAO Chih-Pin</creator><scope>EVB</scope></search><sort><creationdate>20170330</creationdate><title>SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURES AND MANUFACTURING METHOD THEREOF</title><author>CHAO Yuan-Shun ; CHEN Hou-Yu ; TSAO Chih-Pin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2017092770A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHAO Yuan-Shun</creatorcontrib><creatorcontrib>CHEN Hou-Yu</creatorcontrib><creatorcontrib>TSAO Chih-Pin</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHAO Yuan-Shun</au><au>CHEN Hou-Yu</au><au>TSAO Chih-Pin</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURES AND MANUFACTURING METHOD THEREOF</title><date>2017-03-30</date><risdate>2017</risdate><abstract>A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. The fin structure has a top surface and side surfaces and the top surface is located at a height H0 measured from the substrate. An insulating layer is formed over the fin structure and the substrate. In the first recessing, the insulating layer is recessed to a height T1 from the substrate, so that an upper portion of the fin structure is exposed from the insulating layer. A semiconductor layer is formed over the exposed upper portion. After forming the semiconductor layer, in the second recessing, the insulating layer is recessed to a height T2 from the substrate, so that a middle portion of the fin structure is exposed from the insulating layer. A gate structure is formed over the upper portion with the semiconductor layer and the exposed middle portion of the fin structure.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2017092770A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURES AND MANUFACTURING METHOD THEREOF
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-09T21%3A06%3A48IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHAO%20Yuan-Shun&rft.date=2017-03-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2017092770A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true