NUMA SCHEDULING USING INTER-VCPU MEMORY ACCESS ESTIMATION
In a system having non-uniform memory access architecture, with a plurality of nodes, memory access by entities such as virtual CPUs is estimated by invalidating a selected sub-set of memory units, and then detecting and compiling access statistics, for example by counting the page faults that arise...
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| creator | MILOUCHEV Alexandre ZAROO Puneet VENKATASUBRAMANIAN Rajesh |
| description | In a system having non-uniform memory access architecture, with a plurality of nodes, memory access by entities such as virtual CPUs is estimated by invalidating a selected sub-set of memory units, and then detecting and compiling access statistics, for example by counting the page faults that arise when any virtual CPU accesses an invalidated memory unit. The entities, or pairs of entities, may then be migrated or otherwise co-located on the node for which they have greatest memory locality. |
| format | Patent |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | NUMA SCHEDULING USING INTER-VCPU MEMORY ACCESS ESTIMATION |
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