TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT
An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | RENGARAJAN Krishnan S POTLADHURTHI Eswararao CHANDRA Dinesh REDDY Dhani Reddy Sreenivasula |
| description | An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2017004876A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2017004876A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2017004876A13</originalsourceid><addsrcrecordid>eNrjZHAOCfVzdPJxVfBzdXcM8QxzVXDyDPHx9HNVCA_yDHFVcAwO9gwOUXD0c1Fw8vcHsUJCXP1CgUr9_RScPYOcQz1DeBhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGhuYGBiYW5maOhMXGqAPAtLKQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT</title><source>esp@cenet</source><creator>RENGARAJAN Krishnan S ; POTLADHURTHI Eswararao ; CHANDRA Dinesh ; REDDY Dhani Reddy Sreenivasula</creator><creatorcontrib>RENGARAJAN Krishnan S ; POTLADHURTHI Eswararao ; CHANDRA Dinesh ; REDDY Dhani Reddy Sreenivasula</creatorcontrib><description>An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170105&DB=EPODOC&CC=US&NR=2017004876A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170105&DB=EPODOC&CC=US&NR=2017004876A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>RENGARAJAN Krishnan S</creatorcontrib><creatorcontrib>POTLADHURTHI Eswararao</creatorcontrib><creatorcontrib>CHANDRA Dinesh</creatorcontrib><creatorcontrib>REDDY Dhani Reddy Sreenivasula</creatorcontrib><title>TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT</title><description>An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAOCfVzdPJxVfBzdXcM8QxzVXDyDPHx9HNVCA_yDHFVcAwO9gwOUXD0c1Fw8vcHsUJCXP1CgUr9_RScPYOcQz1DeBhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGhuYGBiYW5maOhMXGqAPAtLKQ</recordid><startdate>20170105</startdate><enddate>20170105</enddate><creator>RENGARAJAN Krishnan S</creator><creator>POTLADHURTHI Eswararao</creator><creator>CHANDRA Dinesh</creator><creator>REDDY Dhani Reddy Sreenivasula</creator><scope>EVB</scope></search><sort><creationdate>20170105</creationdate><title>TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT</title><author>RENGARAJAN Krishnan S ; POTLADHURTHI Eswararao ; CHANDRA Dinesh ; REDDY Dhani Reddy Sreenivasula</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2017004876A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>RENGARAJAN Krishnan S</creatorcontrib><creatorcontrib>POTLADHURTHI Eswararao</creatorcontrib><creatorcontrib>CHANDRA Dinesh</creatorcontrib><creatorcontrib>REDDY Dhani Reddy Sreenivasula</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>RENGARAJAN Krishnan S</au><au>POTLADHURTHI Eswararao</au><au>CHANDRA Dinesh</au><au>REDDY Dhani Reddy Sreenivasula</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT</title><date>2017-01-05</date><risdate>2017</risdate><abstract>An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US2017004876A1 |
| source | esp@cenet |
| subjects | INFORMATION STORAGE PHYSICS STATIC STORES |
| title | TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-10T12%3A17%3A11IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=RENGARAJAN%20Krishnan%20S&rft.date=2017-01-05&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2017004876A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |