METHODS AND APPARATUS FOR SIGNAL FLOW GRAPH PIPELINING IN AN ARRAY PROCESSING UNIT THAT REDUCES STORAGE OF TEMPORARY VARIABLES

A system for pipelining signal flow graphs by a plurality of shared memory processors organized in a 3D physical arrangement with the memory overlaid on the processor nodes that reduces storage of temporary variables. A group function formed by two or more instructions to specify two or more parts o...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	Pechanek Gerald George
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!