SYSTEM, APPARATUS, AND METHOD FOR TEMPORARY LOAD INSTRUCTION

SYSTEM, APPARATUS, AND METHOD FOR TEMPORARY LOAD INSTRUCTION

A transient load instruction for a processor may include a transient or temporary load instruction that is executed in parallel with a plurality of input operands. The temporary load instruction loads a memory value into a temporary location for use within the instruction packet. According to some e...

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Hauptverfasser: GOLAB Jakub Pawel, MAHURIN Eric
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator GOLAB Jakub Pawel
MAHURIN Eric
description A transient load instruction for a processor may include a transient or temporary load instruction that is executed in parallel with a plurality of input operands. The temporary load instruction loads a memory value into a temporary location for use within the instruction packet. According to some examples, a VLIW based microprocessor architecture may include a temporary cache for use in writing/reading a temporary memory value during a single VLIW packet cycle. The temporary cache is different from the normal register bank that does not allow writing and then reading the value just written during the same VLIW packet cycle.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title SYSTEM, APPARATUS, AND METHOD FOR TEMPORARY LOAD INSTRUCTION
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