DATA STREAMING SCHEDULER FOR DUAL CHIPSET ARCHITECTURES THAT INCLUDES A HIGH PERFORMANCE CHIPSET AND A LOW PERFORMANCE CHIPSET

A dual chipset architecture, a method of operating a scheduler for a dual chipset architecture, and a computer program product for operating a scheduler for a dual chipset architecture. In an embodiment, the dual chipset architecture comprises a high performance processor, a low performance processo...

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Hauptverfasser:	Folco Rafael Camarda Silva, Leitão Breno Henrique, Santos Tiago Nunes Dos, Araújo Murilo Opsfelder
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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creator	Folco Rafael Camarda Silva Leitão Breno Henrique Santos Tiago Nunes Dos Araújo Murilo Opsfelder
description	A dual chipset architecture, a method of operating a scheduler for a dual chipset architecture, and a computer program product for operating a scheduler for a dual chipset architecture. In an embodiment, the dual chipset architecture comprises a high performance processor, a low performance processor, and a scheduler for the processors. The scheduler is provided for determining an expected data traffic flow to the chipset, and for selectively enabling the high and low performance processors, based on this expected data flow, ahead of this expected data flow reaching the chipset. In one embodiment, a specified data traffic indicator is associated with the expected data traffic flow, and the scheduler uses this specified data traffic indicator to determine the expected data traffic flow. In an embodiment, this specified data traffic indicator is a value for a defined window size for the expected data flow.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2016330126A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2016330126A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2016330126A13</originalsourceid><addsrcrecordid>eNqNiz0LwjAURbM4iPofHjgL_YDuj-S1CaRpSV5wLEXiJFqos7_dDIKLg9O9l3PPVrwUMkJgT9gb10GQmlS05KEdPKiIFqQ2YyAG9LkxSY6eArBGBuOkjSovBG06DSP5rPXoJH01pzK2w_kX3YvNdb6t6fDJnTi2xFKf0vKY0rrMl3RPzymGqiibui7KqsGy_u_1BrgBPDI</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>DATA STREAMING SCHEDULER FOR DUAL CHIPSET ARCHITECTURES THAT INCLUDES A HIGH PERFORMANCE CHIPSET AND A LOW PERFORMANCE CHIPSET</title><source>esp@cenet</source><creator>Folco Rafael Camarda Silva ; Leitão Breno Henrique ; Santos Tiago Nunes Dos ; Araújo Murilo Opsfelder</creator><creatorcontrib>Folco Rafael Camarda Silva ; Leitão Breno Henrique ; Santos Tiago Nunes Dos ; Araújo Murilo Opsfelder</creatorcontrib><description>A dual chipset architecture, a method of operating a scheduler for a dual chipset architecture, and a computer program product for operating a scheduler for a dual chipset architecture. In an embodiment, the dual chipset architecture comprises a high performance processor, a low performance processor, and a scheduler for the processors. The scheduler is provided for determining an expected data traffic flow to the chipset, and for selectively enabling the high and low performance processors, based on this expected data flow, ahead of this expected data flow reaching the chipset. In one embodiment, a specified data traffic indicator is associated with the expected data traffic flow, and the scheduler uses this specified data traffic indicator to determine the expected data traffic flow. In an embodiment, this specified data traffic indicator is a value for a defined window size for the expected data flow.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20161110&DB=EPODOC&CC=US&NR=2016330126A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20161110&DB=EPODOC&CC=US&NR=2016330126A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Folco Rafael Camarda Silva</creatorcontrib><creatorcontrib>Leitão Breno Henrique</creatorcontrib><creatorcontrib>Santos Tiago Nunes Dos</creatorcontrib><creatorcontrib>Araújo Murilo Opsfelder</creatorcontrib><title>DATA STREAMING SCHEDULER FOR DUAL CHIPSET ARCHITECTURES THAT INCLUDES A HIGH PERFORMANCE CHIPSET AND A LOW PERFORMANCE CHIPSET</title><description>A dual chipset architecture, a method of operating a scheduler for a dual chipset architecture, and a computer program product for operating a scheduler for a dual chipset architecture. In an embodiment, the dual chipset architecture comprises a high performance processor, a low performance processor, and a scheduler for the processors. The scheduler is provided for determining an expected data traffic flow to the chipset, and for selectively enabling the high and low performance processors, based on this expected data flow, ahead of this expected data flow reaching the chipset. In one embodiment, a specified data traffic indicator is associated with the expected data traffic flow, and the scheduler uses this specified data traffic indicator to determine the expected data traffic flow. In an embodiment, this specified data traffic indicator is a value for a defined window size for the expected data flow.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNiz0LwjAURbM4iPofHjgL_YDuj-S1CaRpSV5wLEXiJFqos7_dDIKLg9O9l3PPVrwUMkJgT9gb10GQmlS05KEdPKiIFqQ2YyAG9LkxSY6eArBGBuOkjSovBG06DSP5rPXoJH01pzK2w_kX3YvNdb6t6fDJnTi2xFKf0vKY0rrMl3RPzymGqiibui7KqsGy_u_1BrgBPDI</recordid><startdate>20161110</startdate><enddate>20161110</enddate><creator>Folco Rafael Camarda Silva</creator><creator>Leitão Breno Henrique</creator><creator>Santos Tiago Nunes Dos</creator><creator>Araújo Murilo Opsfelder</creator><scope>EVB</scope></search><sort><creationdate>20161110</creationdate><title>DATA STREAMING SCHEDULER FOR DUAL CHIPSET ARCHITECTURES THAT INCLUDES A HIGH PERFORMANCE CHIPSET AND A LOW PERFORMANCE CHIPSET</title><author>Folco Rafael Camarda Silva ; Leitão Breno Henrique ; Santos Tiago Nunes Dos ; Araújo Murilo Opsfelder</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2016330126A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>Folco Rafael Camarda Silva</creatorcontrib><creatorcontrib>Leitão Breno Henrique</creatorcontrib><creatorcontrib>Santos Tiago Nunes Dos</creatorcontrib><creatorcontrib>Araújo Murilo Opsfelder</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Folco Rafael Camarda Silva</au><au>Leitão Breno Henrique</au><au>Santos Tiago Nunes Dos</au><au>Araújo Murilo Opsfelder</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DATA STREAMING SCHEDULER FOR DUAL CHIPSET ARCHITECTURES THAT INCLUDES A HIGH PERFORMANCE CHIPSET AND A LOW PERFORMANCE CHIPSET</title><date>2016-11-10</date><risdate>2016</risdate><abstract>A dual chipset architecture, a method of operating a scheduler for a dual chipset architecture, and a computer program product for operating a scheduler for a dual chipset architecture. In an embodiment, the dual chipset architecture comprises a high performance processor, a low performance processor, and a scheduler for the processors. The scheduler is provided for determining an expected data traffic flow to the chipset, and for selectively enabling the high and low performance processors, based on this expected data flow, ahead of this expected data flow reaching the chipset. In one embodiment, a specified data traffic indicator is associated with the expected data traffic flow, and the scheduler uses this specified data traffic indicator to determine the expected data traffic flow. In an embodiment, this specified data traffic indicator is a value for a defined window size for the expected data flow.</abstract><oa>free_for_read</oa></addata></record>
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title	DATA STREAMING SCHEDULER FOR DUAL CHIPSET ARCHITECTURES THAT INCLUDES A HIGH PERFORMANCE CHIPSET AND A LOW PERFORMANCE CHIPSET
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