FLIP-FLOP STRUCTURE
A flip-flop structure comprising a master latch and a slave latch. An output of an input stage of the master latch is coupled to the output of the master latch. The input stage is arranged to drive a logical state at the output of the master latch corresponding to a logical state of the received dat...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | KORNILOV Alexander Ivanovich KOROLEV Vasily Vladimirovich MIKHAILOV Victor Mikhailovich |
description | A flip-flop structure comprising a master latch and a slave latch. An output of an input stage of the master latch is coupled to the output of the master latch. The input stage is arranged to drive a logical state at the output of the master latch corresponding to a logical state of the received data input signal during a first phase of a clock signal. A feedback component is arranged to sample a logical state at the output of the master latch and to drive a logical state at the output of the master latch based on the sampled logical state at the output of the master latch such that the sampled logical state is maintained, during a second phase of the clock signal. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2016301392A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2016301392A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2016301392A13</originalsourceid><addsrcrecordid>eNrjZBB28_EM0HXz8Q9QCA4JCnUOCQ1y5WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgaGZsYGhsaWRo6GxsSpAgDhBB9e</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>FLIP-FLOP STRUCTURE</title><source>esp@cenet</source><creator>KORNILOV Alexander Ivanovich ; KOROLEV Vasily Vladimirovich ; MIKHAILOV Victor Mikhailovich</creator><creatorcontrib>KORNILOV Alexander Ivanovich ; KOROLEV Vasily Vladimirovich ; MIKHAILOV Victor Mikhailovich</creatorcontrib><description>A flip-flop structure comprising a master latch and a slave latch. An output of an input stage of the master latch is coupled to the output of the master latch. The input stage is arranged to drive a logical state at the output of the master latch corresponding to a logical state of the received data input signal during a first phase of a clock signal. A feedback component is arranged to sample a logical state at the output of the master latch and to drive a logical state at the output of the master latch based on the sampled logical state at the output of the master latch such that the sampled logical state is maintained, during a second phase of the clock signal.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20161013&DB=EPODOC&CC=US&NR=2016301392A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25555,76308</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20161013&DB=EPODOC&CC=US&NR=2016301392A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KORNILOV Alexander Ivanovich</creatorcontrib><creatorcontrib>KOROLEV Vasily Vladimirovich</creatorcontrib><creatorcontrib>MIKHAILOV Victor Mikhailovich</creatorcontrib><title>FLIP-FLOP STRUCTURE</title><description>A flip-flop structure comprising a master latch and a slave latch. An output of an input stage of the master latch is coupled to the output of the master latch. The input stage is arranged to drive a logical state at the output of the master latch corresponding to a logical state of the received data input signal during a first phase of a clock signal. A feedback component is arranged to sample a logical state at the output of the master latch and to drive a logical state at the output of the master latch based on the sampled logical state at the output of the master latch such that the sampled logical state is maintained, during a second phase of the clock signal.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBB28_EM0HXz8Q9QCA4JCnUOCQ1y5WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgaGZsYGhsaWRo6GxsSpAgDhBB9e</recordid><startdate>20161013</startdate><enddate>20161013</enddate><creator>KORNILOV Alexander Ivanovich</creator><creator>KOROLEV Vasily Vladimirovich</creator><creator>MIKHAILOV Victor Mikhailovich</creator><scope>EVB</scope></search><sort><creationdate>20161013</creationdate><title>FLIP-FLOP STRUCTURE</title><author>KORNILOV Alexander Ivanovich ; KOROLEV Vasily Vladimirovich ; MIKHAILOV Victor Mikhailovich</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2016301392A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>KORNILOV Alexander Ivanovich</creatorcontrib><creatorcontrib>KOROLEV Vasily Vladimirovich</creatorcontrib><creatorcontrib>MIKHAILOV Victor Mikhailovich</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KORNILOV Alexander Ivanovich</au><au>KOROLEV Vasily Vladimirovich</au><au>MIKHAILOV Victor Mikhailovich</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>FLIP-FLOP STRUCTURE</title><date>2016-10-13</date><risdate>2016</risdate><abstract>A flip-flop structure comprising a master latch and a slave latch. An output of an input stage of the master latch is coupled to the output of the master latch. The input stage is arranged to drive a logical state at the output of the master latch corresponding to a logical state of the received data input signal during a first phase of a clock signal. A feedback component is arranged to sample a logical state at the output of the master latch and to drive a logical state at the output of the master latch based on the sampled logical state at the output of the master latch such that the sampled logical state is maintained, during a second phase of the clock signal.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2016301392A1 |
source | esp@cenet |
subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
title | FLIP-FLOP STRUCTURE |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T21%3A01%3A12IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KORNILOV%20Alexander%20Ivanovich&rft.date=2016-10-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2016301392A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |