CLOCK-DOMAIN-CROSSING SPECIFIC DESIGN MUTATIONS TO MODEL SILICON BEHAVIOR AND MEASURE VERIFICATION ROBUSTNESS

Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be id...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Gupta Namit K, Narwade Mahantesh D, Forey Jean-Marc A, Toma Horia A
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	Gupta Namit K Narwade Mahantesh D Forey Jean-Marc A Toma Horia A
description	Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of a circuit verification test suite.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2016292331A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2016292331A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2016292331A13</originalsourceid><addsrcrecordid>eNqNy78KwjAQgPEuDqK-w4FzwbYgOKbJtR42OcklXUuROPmnUN8fUXwAp2_5fsvsrjvWp9ywVeRy7VmEXAtyRk0NaTAo1DqwMahA7AQCg2WDHQh1pNlBjUfVE3tQzoBFJdEj9Og__GvAcx0lOBRZZ4vreJvT5tdVtm0w6GOepueQ5mm8pEd6DVHKXbEvD2VVFaqo_rveMuc4QQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CLOCK-DOMAIN-CROSSING SPECIFIC DESIGN MUTATIONS TO MODEL SILICON BEHAVIOR AND MEASURE VERIFICATION ROBUSTNESS</title><source>esp@cenet</source><creator>Gupta Namit K ; Narwade Mahantesh D ; Forey Jean-Marc A ; Toma Horia A</creator><creatorcontrib>Gupta Namit K ; Narwade Mahantesh D ; Forey Jean-Marc A ; Toma Horia A</creatorcontrib><description>Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of a circuit verification test suite.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20161006&DB=EPODOC&CC=US&NR=2016292331A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20161006&DB=EPODOC&CC=US&NR=2016292331A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Gupta Namit K</creatorcontrib><creatorcontrib>Narwade Mahantesh D</creatorcontrib><creatorcontrib>Forey Jean-Marc A</creatorcontrib><creatorcontrib>Toma Horia A</creatorcontrib><title>CLOCK-DOMAIN-CROSSING SPECIFIC DESIGN MUTATIONS TO MODEL SILICON BEHAVIOR AND MEASURE VERIFICATION ROBUSTNESS</title><description>Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of a circuit verification test suite.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNy78KwjAQgPEuDqK-w4FzwbYgOKbJtR42OcklXUuROPmnUN8fUXwAp2_5fsvsrjvWp9ywVeRy7VmEXAtyRk0NaTAo1DqwMahA7AQCg2WDHQh1pNlBjUfVE3tQzoBFJdEj9Og__GvAcx0lOBRZZ4vreJvT5tdVtm0w6GOepueQ5mm8pEd6DVHKXbEvD2VVFaqo_rveMuc4QQ</recordid><startdate>20161006</startdate><enddate>20161006</enddate><creator>Gupta Namit K</creator><creator>Narwade Mahantesh D</creator><creator>Forey Jean-Marc A</creator><creator>Toma Horia A</creator><scope>EVB</scope></search><sort><creationdate>20161006</creationdate><title>CLOCK-DOMAIN-CROSSING SPECIFIC DESIGN MUTATIONS TO MODEL SILICON BEHAVIOR AND MEASURE VERIFICATION ROBUSTNESS</title><author>Gupta Namit K ; Narwade Mahantesh D ; Forey Jean-Marc A ; Toma Horia A</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2016292331A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>Gupta Namit K</creatorcontrib><creatorcontrib>Narwade Mahantesh D</creatorcontrib><creatorcontrib>Forey Jean-Marc A</creatorcontrib><creatorcontrib>Toma Horia A</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Gupta Namit K</au><au>Narwade Mahantesh D</au><au>Forey Jean-Marc A</au><au>Toma Horia A</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CLOCK-DOMAIN-CROSSING SPECIFIC DESIGN MUTATIONS TO MODEL SILICON BEHAVIOR AND MEASURE VERIFICATION ROBUSTNESS</title><date>2016-10-06</date><risdate>2016</risdate><abstract>Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of a circuit verification test suite.</abstract><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_US2016292331A1
source	esp@cenet
subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
title	CLOCK-DOMAIN-CROSSING SPECIFIC DESIGN MUTATIONS TO MODEL SILICON BEHAVIOR AND MEASURE VERIFICATION ROBUSTNESS
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-21T16%3A39%3A10IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Gupta%20Namit%20K&rft.date=2016-10-06&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2016292331A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true